Applicability of extreme ultraviolet lithography to fabrication of half pitch 35nm interconnects

Aoyama, Hajime; Tanaka, Yuusuke; Tawarayama, Kazuo; Nakamura, Norimasa; Soda, E.; Oda, Noriaki; Arisawa, Yukiyasu; Uno, Taiga; Kamo, Takashi; Matsunaga, Kentaro; Kawamura, Daisuke; Tanaka, Toshihiko; Tanaka, Hiroyuki; Saito, Shuichi; Mori, Ikue

doi:10.1117/12.846325

Cited by 16 publications

(8 citation statements)

References 18 publications

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“…Extreme Ultraviolet Lithography (EUVL) is one of the most promising Next Generation Lithography (NGL) technologies since the ten times reduction in wavelength in EUVL offers the capability of a continuation of Moore's law beyond the 22 nm technology node [1,17]. However, the used light of 13.5 nm wavelength is not transmitted, but absorbed by most of materials, and thus only reflective optical components and masks can be used.…”

Section: Introductionmentioning

confidence: 99%

Simultaneous flare level and flare variation minimization with dummification in EUVL

Fang

Chang

2012

Proceedings of the 49th Annual Design Automation Conference

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Extreme Ultraviolet Lithography (EUVL) is one of the most promising Next Generation Lithography (NGL) technologies. Due to the surface roughness of the optical system used in EUVL, the rather high level of flare (i.e., scattered light) becomes one of the most critical issues in EUVL. In addition, the layout density nonuniformity and the flare periphery effect (the flare distribution at the periphery is much different from that in the center of a chip) also induce a large flare variation within a layout. Both of the high flare level and the large flare variation could worsen the control of critical dimension (CD) uniformity. Dummification (i.e., tiling or dummy fill) is one of the flare compensation strategies to reduce the flare level and the flare variation for the process with a clear-field mask in EUVL. However, existing dummy fill algorithms for Chemical-Mechanical Polishing (CMP) are not adequate for the flare mitigation problem in EUVL due to the flare periphery effect. This paper presents the first work that solves the flare mitigation problem in EUVL with a specific dummification algorithm flow considering global flare distribution. The dummification process is guided by dummy demand maps, which are generated by using a quasi-inverse lithography technique. In addition, an error-controlled fast flare map computation technique is proposed and integrated into our algorithm to further improve the efficiency without loss of computation accuracy. Experimental results show that our flow can effectively and efficiently reduce the flare level and the flare variation, which may contribute to the better control of CD uniformity.

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Section: Introductionmentioning

confidence: 99%

Simultaneous flare level and flare variation minimization with dummification in EUVL

Fang

Chang

2012

Proceedings of the 49th Annual Design Automation Conference

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“…Here, we conducted a yield analysis for hp-3x-nm and hp-2x-nm test chips by using the EUV1 (Nikon) full-field exposure tool 9,10 . A higher yield on hp-3x-nm test chips was achieved through the application of various resist materials and the improvement of resist processes.…”

Section: Introductionmentioning

confidence: 99%

Development status of EUV resist materials and processing at Selete

Matsunaga¹,

Shiraishi²,

Santillian³

et al. 2011

SPIE Proceedings

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The Selete R&D program evaluates the feasibility of the Extreme ultraviolet (EUV) lithography process for manufacturing semiconductor devices. We therefore conducted a yield analysis of hp-2x-nm test chips by using the EUV1 (Nikon) full-field exposure tool. However, the resist performance did not comply with the stringent requirements of ultimate resolution, sensitivity, and line-width roughness.We subsequently reported two new Selete standard resists (SSRs), i.e., SSR6 and SSR7. SSR6 is the polymer resist used in hp-2x-nm test chip evaluation in which an ultimate resolution of 22 nm line-and-space (L/S) pattern was achieved. SSR7 is the first molecular resist that was evaluated for feasibility at Selete. SSR7 is a fullerene based resist with strong etching durability. By using this resist, an ultimate resolution of 24 nm L/S pattern was achieved.We have also evaluated resist processing by using SSRs for hp-2x-nm test chip evaluation. An ultrathin underlayer was evaluated for the improvement of pattern transferability. This optimized ultrathin underlayer was coated on the test chip substrate that was devoid of nano-sized-pinholes, and a fine pattern was observed on this ultrathin underlayer. In the evaluation of the development process, SSRs were evaluated with tetramethylammonium hydroxide (TMAH) and tetrabutylammonium hydroxide (TBAH) developer solutions. In summary, it was clear that the lithographic performance improvement varies depending on the type of polymer resist used with a particular developer solution. Furthermore, a significant improvement in the prevention of pattern collapse was demonstrated using a combination of the TBAH developer solution and alternative rinse solutions.

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“…Table 1 shows the process conditions used in this evaluation. Selete standard resist 4 (SSR4), Selete standard resist 5 (SSR5) and Selete standard resist 6 (SSR6) were coated on 300mm Si substrate and exposed by full-field exposure tool (EUV1: Nikon) in Selete [6][7][8] . And the samples were developed with SOKUDO Track.…”

Section: Introductionmentioning

confidence: 99%

Study of post-develop defect on typical EUV resist

Harumoto¹,

Suyama²,

Miyagi³

et al. 2011

SPIE Proceedings

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This study reports on post-develop defect for EUV resist process. Presently, research and development of EUV resists are continuously being carried out in terms of resolution, sensitivity, LWR [1,2] . However, in the preparation of EUV lithography for mass-production, research on the reduction of pattern defects, especially post-develop defect is also necessary. As observed during the early stages of resist development for the various lithographic technologies, a large number of pattern defects are commonly coming from the resist dissolution process.As previously reported, utilizing an EUV exposure tool, we have classified several EUV specific defects on exposed and un-exposed area. And also we have reported approaches of defect reduction. [3] In this work, using some types developer solution (TBAH, TBAH+, etc) comparing with current developer solution (TMAH), EUV specific defects were evaluated. Furthermore, we investigated the defect appearing-mechanism and approached defect reduction by track process. Finally, based on these results, the direction of defect reduction approaches applicable for EUV resist processing was discussed.

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Applicability of extreme ultraviolet lithography to fabrication of half pitch 35nm interconnects

Cited by 16 publications

References 18 publications

Simultaneous flare level and flare variation minimization with dummification in EUVL

Simultaneous flare level and flare variation minimization with dummification in EUVL

Development status of EUV resist materials and processing at Selete

Study of post-develop defect on typical EUV resist

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