Third Generation Partnership Project (3GPP) Long Term Evolution (LTE) system is targeted to efficiently guarantee the quality of service (QoS) of services such as audio/video streaming, gaming and Voice over IP (VoIP). So the system resource allocation should obtain the multiuser diversity gain making full use of the channel condition, and take the quality of service (QoS) of different services into account. Due to the heavy user's space and limited Resource Block (RBs), it is infeasible to guarantee all ongoing users' QoS. Then, some call are blocked and lost. The proposed method reduces the handoff blocking probability in LTE wireless networks. Hybrid Adaptive call admission control scheme performs the QoS operation based on the priority at the time of call admission. This method reduces new call blocking probability.

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Power dissipation during testing of VLSI circuits is major concern due to the switching activity of the circuit under test. In this paper, a novel method is presented, that aims at reducing total power consumption in combinational circuit during testing. This is achieved by minimizing the switching activity of the circuit by reducing the Hamming Distance between successive test vectors. The test vectors are generated with don't care for particular circuit. These vectors are reordered for minimum total hamming distance. Don't care bits of these vectors are replaced by appropriate value 1 or 0 so that the total number of transitions between two vectors is minimum. Then the same vector set is used for testing. Thus the reordered test vector set reduces testing power without affecting the fault coverage. Experimental results of the proposed method with ISCAS85 benchmark circuits show that the switching activity can be reduced up to 35 % when compared to the previous research paper of this work [2] and reduced up to 91% when compared with [6,7].

Memristor is a newly found fourth circuit element for the next generation emerging nonvolatile memory technology. In this paper, design of new type of nonvolatile static random access memory cell is proposed by using a combination of memristor and complemented metal oxide semiconductor. Biolek memristor model and CMOS 180 nm technology are used to form a single cell. By introducing distinct binary logic to avoid safety margin is left for each binary logic output and enables better read/write data integrity. The total power consumption reduces from 0.407 mw (milli-watt) to 0.127 mw which is less than existing memristor based memory cell of the same CMOS technology. Read and write time is also significantly reduced. However, write time is higher than conventional 6T SRAM cell and can be reduced by increasing motion of electron in the memristor. The change of the memristor state is shown by applying piecewise linear input voltage.

Human action recognition is an essential process in surveillance video analysis, which is used to understand the behavior of people to ensure safety. Most of the existing methods for HAR use computationally heavy networks such as 3D CNN and two-stream networks. To alleviate the challenges in the implementation and training of 3D deep learning networks, which have more parameters, a customized lightweight directed acyclic graph-based residual 2D CNN with fewer parameters was designed from scratch and named HARNet. A novel pipeline for the construction of spatial motion data from raw video input is presented for the latent representation learning of human actions. The constructed input is fed to the network for simultaneous operation over spatial and motion information in a single stream, and the latent representation learned at the fully connected layer is extracted and fed to the conventional machine learning classifiers for action recognition. The proposed work was empirically verified, and the experimental results were compared with those for existing methods. The results show that the proposed method outperforms state-of-the-art (SOTA) methods with a percentage improvement of 2.75% on UCF101, 10.94% on HMDB51, and 0.18% on the KTH dataset.