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An innovative in-situ electronic package assembly process is presented using the on-chip power to cure the package thermal interface and seal materials and to verify the thermal performance of the electronic package. The in-situ curing process was thermally modeled to demonstrate that the thermal interface and seal materials would reach their required curing temperatures by controlling the chip power and heat sink air flow. Experimental validation of the in-situ cure method was conducted using thermal test vehicles. Thermal resistance characterization of the in-situ cured package in comparison to a batch oven cured package showed better thermal performance stability with increasing temperature.

Laminates or sequential build-up (SBU) laminate comprised of dielectric materials, metal traces, and metal vias not only serve as the mechanical support for the silicon integrated circuits (ICs), but also electrically connect ICs to ball grid array (BGA); by way of an embedded power delivery structure. Electrical current required to power the ICs is carried through spatially distributed metal traces and vias. The non-uniformity in the power distribution may induce hotspots due to parasitic Ohmic heating; especially in regions with high current density. Electrical packaging engineers need effective tools to identify, quantify, and mitigate hot spots in the laminate. Thermoelectrical multiphysical simulation provides a robust platform integrating the electrical, and thermal analyses for the study of joule heating in a complex design. Conventional simulations simplify detailed laminate wiring layout as a single planar with effective orthogonal material properties. Such simplification provides a solution to the inherent simulation challenges encountered with a complex design (i.e. tiny characteristic lengths, high aspect ratios, excessive computational time and resources). However, simplification comes with a price. Information required to optimize the detail trace and via wiring physical design is unavailable in a solution incorporating an effective laminate; laminate joule heating as well as non-uniform trace wiring are left out. The laminate temperature profile is averaged based on effective material properties. Without accurate joule heating evaluation, the hotspots cannot be identified or quantified. Overheating inside the laminate compromises signal speed and integrity, raises reliability concerns, and may even trigger catastrophic damage of dielectric material breakdown. This work introduces an iterative approach integrating the detailed laminate electrical computer aided design (ECAD) and package design to simulate the joule heating with minimum simplification. The iterative loop enables constant update of temperature (thru thermal simulation platform) and power distribution (thru electrical simulation platform) in each trace layer and via. An accurate temperature dependent Joule Heating assessment is achieved upon convergence. The solution captures the dependence on temperature of the material properties and of the Joule heating itself. The package level structure including an IC with a power map is incorporated to simulate in-situ package operating condition. After thorough investigation and analyses of laminate joule heating phenomena under different conditions, a predictive curve for maximum temperature rise percentage has been proposed to guide laminate wiring layout physical design and optimization. A ratio exceeding 4–5% joule heating to IC power is recommended as the check point for simulation to assess laminate overheating issues with detailed trace layout information.