Optical transient current spectroscopy (OTCS) is a member of the class of deep level transient spectroscopy (DLTS) techniques. Its advantage is that, unlike other DLTS techniques, it can be applied to semi‐insulating normalGaAs (which is the starting material for integrated circuit (IC) fabrication). The aim is to obtain information on deep trapping levels, which may be of fundamental interest and is certainly of practical interest since it can help in diagnosing the suitability of the material for IC fabrication. We have investigated the method using different device geometries, electrode materials, surface preparations, and normalGaAs crystals. Various “peaks” in the OTCS spectrum were identified, including EL2, the center responsible for the semi‐insulating property in undoped LEC normalGaAs . One is of particular interest, since it is a negative peak, i.e., the current increases (instead of decreasing) with time (after the sudden drop when the light ceases) until it settles at its steady‐state dark value. The amplitude of this peak was found to be much bigger with thinned sandwich normalmetal/normalGaAs/normalmetal structures than with planar electrode structures. Evidence was obtained that this peak is associated with crystal damage produced by abrasion or polishing. The current theory of OTCS due to Hurtes et al. and Martin et al. is based on the Sah et al. treatment of depletion regions. It is pointed out that it may not necessarily apply with typical electrode geometries. In particular, the model that this theory provides for negative peaks is not the only possible one. Two further models are proposed. Negative peaks could be due to an electrically neutral semiconductor model in which more majority carriers are trapped due to illumination. They could also be given by an insulator model in which the current is due to thermal release of carriers from traps that then travel a certain way before recapture.

Abstract-This paper presents the first reported joint gate sizing and buffer insertion method for minimizing the delay of power constrained combinational logic networks that can incorporate a mixture of unbuffered and buffered gates (or mixture of CMOS and BiCMOS gates). In the method, buffered gates in a network are decided on by an iterative process that uses a sequence of sizing optimizations where after each sizing optimization an update to the selection of buffered gates is made. In this way, high drive capability buffered (i.e., BiCMOS) gates with sufficiently low fan-out are identified and replaced with a lower power unbuffered (i.e., CMOS) version. As well, the optimality of the final design is assessed based on a lowerbound delay value that is calculated. Experimental results have confirmed the efficiency and utility of the proposed method. In 8-b adder or 8 2 8 b multiplier networks, just two iterations are sufficient to achieve a delay that is at worst within 0.6% of its final optimized value and at worst within 10% of the lowerbound value. In the design of BiCMOS networks, it is seen that a speed advantage (at equivalent power) can be systematically achieved by using a mix of CMOS and BiCMOS gates versus using all CMOS or all BiCMOS gates and that this advantage increases with the tightness of the power constraint and with load capacitance.

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