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The paper concerns a configurable soft core of the 8051 µC implemented in VHDL. The main goal of efforts undertaken during design of the core was the full compatibility with the industrial standards 80C51 and 80C52 on the instruction and timing levels. It doesn't limit flexibility of core's architecture, which can be easily optimized according to the current design constraints. The configuration capabilities of the core are grouped in a configuration package. That approach allows for separation them from the indigenous part of the core, which remains untouched by a user and can be encoded in order to hide the VHDL code. Inside the configuration package there are several constants. Assigning values to them, a user has opportunity to determine the core's structure (types of functional modules used in the core), RAM and ROM sizes, the instruction set, number of interrupted sources, number of execution cycles for division and multiplication, etc.The core is independent of the CPU peripheral modules (e.g. timer/counters, I/O ports, UART, etc.) due to a SFR bus. Peripherals are accessed by the use of special function registers. Upper half of available addresses of the internal RAM is just reserved for them. Hence the communication between the CPU and SFRs is carried out in the same way as in case of memory cells.The core has been proven on silicon. It was applied in the smart pressure sensor chip and an 8031-compatible µC. The compatibility with the industrial was checked on the logic verifier, where original 80C51 and 80C52 chips were applied during tests as references.

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