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Abstract

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Most existing power gating structures provide only one power-saving mode. We propose a novel power gating structure that supports both a cutoff mode and an intermediate powersaving and data-retaining mode. Experiments with test structures fabricated in 0.13-m CMOS bulk technology show that our power gating structure yields an expanded design space with more powerperformance tradeoff alternatives. Index Terms-Deep-submicrometer CMOS, ground bounce noise, low voltage, multi-threshold CMOS (MTCMOS).

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