The next generation of logic gate devices are expected to depend upon radically new technologies mainly due to the increasing difficulties and limitations of existing CMOS technology. MOSFET like CNFETs should ideally be the best devices to work with for high-performance VLSI. This paper presents results of a comprehensive comparative study of MOSFET-like carbon nanotube field effect transistors (CNFETs) technology based logic gate library for high-speed, low-power operation than conventional bulk CMOS libraries. It focuses on comparing four promising logic families namely: complementary-CMOS (C-CMOS), transmission gate (TG), complementary pass logic (CPL) and Domino logic (DL) styles are presented. Based on these logic styles, the proposed library of static and dynamic NAND-NOR logic gates, XOR, multiplexer and full adder functions are implemented efficiently and carefully analyzed with a test bench to measure propagation delay and power dissipation as a function of supply voltage. This analysis provides the right choice of logic style for low-power, high-speed applications. Proposed logic gates libraries are simulated using Synopsys HSPICE based on the standard 32 nm CNFET model. The simulation results demonstrate that, it is best to use C-CMOS logic style gates that are implemented in CNFET technology which are superior in performance compared to other logic styles, because of their low average powerdelay-product (PDP). The analysis also demonstrates how the optimum supply voltage varies with logic styles in ultra-low power systems. The robustness of the proposed logic gate library is also compared with conventional and state-art of CMOS logic gate libraries.

This paper considers a class of fractional-order complex-valued Hopfield neural networks (CVHNNs) with time delay for analyzing the dynamic behaviors such as local asymptotic stability and Hopf bifurcation. In the case of a neural network with hub and ring structure, the stability of the equilibrium state is investigated by analyzing the eigenvalue of the corresponding characteristic matrix for the hub and ring structured fractional-order time delay models using a Laplace transformation for the Caputo-fractional derivatives. Some sufficient conditions are established to guarantee the uniqueness of the equilibrium point. In addition, conditions for the occurrence of a Hopf bifurcation are also presented. Finally, numerical examples are given to demonstrate the effectiveness of the derived results.

In this study, we investigate the problem of multiple Mittag-Leffler stability analysis for fractional-order quaternion-valued neural networks (QVNNs) with impulses. Using the geometrical properties of activation functions and the Lipschitz condition, the existence of the equilibrium points is analyzed. In addition, the global Mittag-Leffler stability of multiple equilibrium points for the impulsive fractional-order QVNNs is investigated by employing the Lyapunov direct method. Finally, simulation is performed to illustrate the effectiveness and validity of the main results obtained.

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