In this paper we proposed a novel enhanced gate diffusion (EGDI) adder is designed and is implemented in Distributed Arithmetic (DA) based Finite Impulse Response (FIR) filter. Generally multipliers, adders and shift accumulators are the basic blocks present in the FIR filters. The hardware architecture of multipliers is very high. To get rid of this, multiplier less architecture are needed in FIR filter. So Distributed Arithmetic architecture place a key role in FIR filters which will occupy less area and increase the speed. To reduce the area further the adders in DA are designed using enhanced gate diffusion (EGDI) which increases the operation speed of FIR filter and at same time the area will be decreased. The proposed design is synthesized and implemented in Synapsis design compiler tool. The area, power delay product, frequency, area delay product and power of the proposed design are calculated. When we observe the synthesis results, the proposed design has 15% high frequency rate when compare with the existing design. Also the proposed design is more useful in signal processing applications like decision feed-back equalizer.