Proposed is a new selective negative word line scheme that yields almost 2.7% of the fail bit count (FBC) in a DRAM chip with a conventional negative word line scheme in the pause refresh state. It has a superior dynamic refresh characteristic, which is almost 0.3% of the FBC in a DRAM chip using the ground word line scheme. This scheme leads to a very low cell V TH (threshold voltage).Introduction: In the DRAM industry, the negative word line (NWL) scheme [1] is presently one of the most representative techniques used for low voltage operation [2][3][4]. However, it also has disadvantages, such as gate-induced drain leakage (GIDL) [5]. We propose a new NWL approach called the 'selective negative word line scheme' (SNWL) [6], which has the advantages of both the conventional NWL and the ground word line (GWL) scheme, even though it has an area penalty of 0.01% for the switching circuits, compared with the NWL scheme.

Thin ZrO2/Ta2O5 multi-laminate layer of ~10 nm was grown by atomic layer deposition (ALD) method and it was discussed about the metallic Ta reduction at the interface between ZrO2 and Ta2O5. Metallic Ta 4f7/2 peak was observed inside of the layer from the result of XPS analysis and it is thought that strong metallic Ta reduction was happened between Ta2O5 and as-coming Zr source (or ZrO2). Also, these results were supported by the Gibbs free energy calculations.