Thermal deposition of n-dopant onto SWCNT sheet (p-type) using patterned mask can fabricate p–n patterns with high special resolution. Thermoelectric generator using patterned SWCNT sheets exhibited power density of 60 nW cm−2 at ΔT = 25 °C.

Temperature increase in the continuously narrowing interconnects accelerates the performance and reliability degradation of very large scale integration (VLSI). Thermal boundary resistance (TBR) between an interconnect metal and dielectric interlayer has been neglected or treated approximately in conventional thermal analyses, resulting in significant uncertainties in performance and reliability. In this study, we investigated the effects of TBR between an interconnect metal and dielectric interlayer on temperature increase of Cu, Co, and Ru interconnects in deeply scaled VLSI. Results indicate that the measured TBR is significantly higher than the values predicted by the diffuse mismatch model and varies widely from 1 × 10 −8 to 1 × 10 −7 m 2 K W −1 depending on the liner/barrier layer used. Finite element method simulations show that such a high TBR can cause a temperature increase of hundreds of degrees in the future VLSI interconnect. Characterization of interface properties shows the significant importance of interdiffusion and adhesion in TBR. For future advanced interconnects, Ru is better than Co for heat dissipation in terms of TBR. This study provides a guideline for the thermal management in deeply scaled VLSI.

Thermoelectric (TE) generators play an important role in preventing an energy crisis and environmental deterioration by converting wasted heat, generated by various human activities, into electrical energy. This work is the first experimental demonstration of a bileg Si-nanowire (Si-NW) micro thermoelectric generator with cavity-free architecture for designing a large-scale integrated planar Si-NW TE generator. In the bileg-TE generator, the mobility and thermopower mismatches between electron and hole effects on the optimum dimensional parameters of n- and p-type Si-NWs and optimum dose of impurity. In this work, under a specific ion dose condition, the best p-type NW width exists at less than 100 nm when the n-type NW width is 60 nm. The experimental dependency of the power density on the p-type NW width is in agreement with the estimation of an equivalent heat-electrical circuit model.

Ruthenium may replace copper interconnects in next-generation very-large-scale integration (VLSI) circuits. However, interfacial bonding between Ru interconnect wires and surrounding dielectrics must be optimized to reduce thermal boundary resistance (TBR) for thermal management. In this study, various adhesion layers are employed to modify bonding at the Ru/SiO2 interface. The TBRs of film stacks are measured using the frequency-domain thermoreflectance technique. TiN and TaN with high nitrogen contents significantly reduce the TBR of the Ru/SiO2 interface compared to common Ti and Ta adhesion layers. The adhesion layer thickness, on the other hand, has only minor effect on TBR when the thickness is within 2–10 nm. Hard X-ray photoelectron spectroscopy of deeply buried layers and interfaces quantitatively reveals that the decrease in TBR is attributed to the enhanced bonding of interfaces adjacent to the TaN adhesion layer, probably due to the electron transfer between the atoms at two sides of the interface. Simulations by a three-dimensional electrothermal finite element method demonstrate that decreasing the TBR leads to a significantly smaller temperature increase in the Ru interconnects. Our findings highlight the importance of TBR in the thermal management of VLSI circuits and pave the way for Ru interconnects to replace the current Cu-based ones.

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