ABSTRACT

Common sub-expression elimination (CSE) serves as a useful optimization technique in the synthesis of arithmetic datapaths described at RTL. However, CSE has a limited potential for optimization when many common sub-expressions are not exposed. Given a suitable transformation of the polynomial system representation, which exposes many common sub-expressions, subsequent CSE can offer a higher degree of optimization. The objective of this paper is to develop algebraic techniques that perform such a transformation, and present a methodology to integrate it with CSE to further enhance the potential for optimization. In our experiments, we show that this integrated approach outperforms conventional methods in deriving areaefficient hardware implementations of polynomial systems. I. IntroductionHigh-level descriptions of arithmetic datapaths that perform polynomial computations over bit-vectors are found in many practical applications, such as in Digital Signal Processing (DSP) for multi-media applications and embedded systems. These polynomial designs are initially specified using behavioural or Register-Transfer-Level (RTL) descriptions, which are subsequently synthesized into hardware using high-level/logic synthesis tools [1]. The growing market for such applications requires sophisticated CAD support for their design, optimization and synthesis.The general area of high-level synthesis has seen extensive research over the years. Various algorithmic techniques have been devised, and CAD tools have been developed that are quite adept at capturing hardware description language (HDL) models and mapping them into control/data-flow graphs (CDFGs), performing scheduling, resource allocation and sharing, binding, retiming, etc., [2]. However, these tools lack the mathematical wherewithal to perform sophisticated algebraic manipulation for arithmetic datapath-intensive designs. Such designs implement a sequence of add, mult type of algebraic computations over bit-vectors; they are generally modeled at RTL or behavioral-level as systems of multi-variate polynomials of finite degree [3] [4]. Hence, there has been increasing interest in exploring the use of algebraic manipulation of polynomial expressions, for RTL synthesis of arithmetic datapaths. Several techniques such as Horner decomposition, factoring with common sub-expression elimination [5], term-rewriting [6], etc., have been proposed. Symbolic computer algebra [3] [4] [7] has also been employed for

Polynomial computations over fixed-size bitvectors are found in many practical datapath designs. For efficient RTL synthesis, it is important to identify good decompositions of the polynomial into smaller/simpler units. Symbolic computer algebra algorithms and tools have been used for this purpose. However, fixed-size (m) bit-vector arithmetic is polynomial algebra over the finite integer ring Z2m , which is a non-unique factorization domain (non-UFD). While non-UFDs provide an extra freedom to search for decompositions, they complicate polynomial manipulation as traditional division-based algorithms are inapplicable. This paper presents new mathematical concepts for polynomial decomposition over Z2m , for RTL synthesis over fixedsize m-bit vectors. Given a polynomial, we identify a specific set of linear expressions and compute the Gröbner bases of their ideal (over non-UFD Z2m) using syzygies. This basis serves as good building-blocks for the given computation. A decomposition is identified by subsequent Gröbner basis reduction. Experimental results demonstrate significant area savings due to our approach, as compared against contemporary datapath synthesis techniques.

Abstract-This paper addresses the problem of solving finite word-length (bit-vector) arithmetic with applications to equivalence verification of arithmetic datapaths. Arithmetic datapath designs perform a sequence of add, mult, shift, compare, concatenate, extract, etc., operations over bit-vectors. We show that such arithmetic operations can be modeled, as constraints, using a system of polynomial functions of the type f :This enables the use of modulo-arithmetic based decision procedures for solving such problems in one unified domain. We devise a decision procedure using Newton's p-adic iteration to solve such arithmetic with composite moduli, while properly accounting for the word-sizes of the operands. We describe our implementation and show how the basic p-adic approach can be improved upon. Experiments are performed over some communication and signal processing designs that perform non-linear and polynomial arithmetic over word-level inputs. Results demonstrate the potential and limitations of our approach, when compared against SAT-based approaches.

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