No abstract

No abstract

Microwave planar sensors employ conventional passive complementary split ring resonators (CSRR) as their sensitive region. In this work, a novel planar reflective sensor is introduced that deploys CSRRs as the front-end sensing element at fres=6 GHz with an extra loss-compensating negative resistance that restores the dissipated power in the sensor that is used in dielectric material characterization. It is shown that the S11 notch of −15 dB can be improved down to −40 dB without loss of sensitivity. An application of this design is shown in discriminating different states of vanadium redox solutions with highly lossy conditions of fully charged V5+ and fully discharged V4+ electrolytes.

The vanadium redox flow battery electrolyte is prone to several capacity loss mechanisms, which must be mitigated to preserve electrolyte health and battery performance. This study investigates a simple and effective technique for the recovery of capacity loss arising from symmetrical mechanisms via automatic electrolyte rebalancing. However, chemical or electrochemical techniques must be used to mitigate capacity loss from asymmetrical mechanisms (e.g., air oxidation of V2+), which requires knowledge of the oxidation states present in the electrolytes. As such, this study assesses the suitability of SOC tracking via electrolyte absorption for independent monitoring of the anolyte and catholyte within an existing VRFB system. Testing is performed over cycling of a 40 cell, 2.5 kW with 40 L of electrolyte. Optical monitoring is performed using a custom-made flow cell with optical paths (interior cavity thicknesses) ranging from 1/4″ to 1/16″. Light transmitted through the cell by a 550 lumen white light source is monitored by a simple photodiode. The electrolyte rebalancing mechanism displayed success in recovering symmetrical capacity losses, while optical monitoring was unsuccessful due to the high absorbance of the electrolyte. Potential improvements to the monitoring system are presented to mitigate this issue.

A highly manufacturable I l0nm Embedded DRAM technology with stack A1,03 MIM capacitor has been demonstrated successfully for the first time. High-density DRAM core with 0.1pm2 cell size and high performance logic circuits have been realized at the same time by separation of the gate pattern at memory cell and peripheral logic region. Low temperature BDL process, highly reliable A124 MIM capacitors have been developed to control process temperature. DRAM cell performance has been improved by introducing tungsten wordline, CoSi, plug and tungsten bitline. 7 levels Cu and CVD-OSG low-k material have been implemented to satisfy the requirement of high performance logic circuits design.