We demonstrated a nanowire gate-all-around (GAA) negative capacitance (NC) tunnel field-effect transistor (TFET) based on the GaAs/InN heterostructure using TCAD simulation. In the gate stacking, we proposed a tri-layer HfO 2 /TiO 2 /HfO 2 as a high-K dielectric and hafnium zirconium oxide (HZO) as a ferroelectric (FE) layer. The proposed GAA-TFET overcomes the thermionic limitation (60 mV/decade) of conventional MOSFETs' subthreshold swing (SS) thanks to its improved electrostatic control and quantum mechanical tunneling. Simultaneously, the NC state of ferroelectric materials improves TFET performance by exploiting differential amplification of the gate voltage under certain conditions. The most surprising discoveries of this device, which outperforms all previous results, are the very high I ON /I OFF ratio on the order of 10 11 and the enormous on-state current of 135 µA. The incorporation of the NC effect with a 9 nm HZO results in the lowest SS of 20.56 mV/dec (52.38% lower than baseline TFET) and the highest voltage gain of 6.58. Furthermore, the output characteristics revealed a large transconductance (g m ) of 7.87 mS (10 3 order higher than the baseline TFET), drain-induced barrier lowering (DIBL) of 9.7 mV, and a threshold voltage of 0.53 V (37.65% lower than baseline TFET), all of which are significant. Thus, all of the results indicate that the proposed device structure may lead to a new route for electronic devices, creating higher speed and lower power consumption.INDEX TERMS BTBT, gate-all-around structure, heterojunction, nanowire tunnel-FET, negative capacitance.

Gate-all-around (GAA) field effect transistors (FETs) have appeared as one of the potential candidates for the electrostatic integrity required to reduce MOSFETs to minimum channel lengths. Meanwhile, the negative capacitance effect of ferroelectrics is known as a remarkable quality enhancer for MOSFETs in terms of reducing sub-threshold slope (SS), supply voltage, and power consumption by utilizing the gate voltage amplification phenomenon. In this work, combining these two phenomena we numerically design a cylindrical GAA NCFET where promising two-dimensional WSe 2 is used as a channel material. We have suggested a high-K dielectric consisting of a tri-layer HfO 2 /TiO 2 /HfO 2 and lead zirconate titanate (PZT) as a ferroelectric layer in the gate stacking. The extremely high I on /I of f ratio on the order of 10 12 (six order higher than conventional FET), and the high on-state current of 119 µA are the most remarkable findings of this device which exceeds all the earlier results. The integration of the NC effect utilizing a 20 nm PZT offers lowest SS of 18.9 mV/dec. Moreover, a large transconductance (g m ) of 117 µS and a higher current cut-off frequency (f T ) of 335 GHz were reported from the output characteristics. These outcomes allude that the suggested device structure may create a new path for electronic devices; therefore, it can be used for high speed operation with low power consumption.

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