Abstract:A 10-Gb/s trans-impedance amplifier (TIA) with insensitive characteristics to photodiode junction capacitance is demonstrated in 0.13-µm CMOS technology. The TIA has LC-ladder input configuration which allows large bandwidth even with large photodiode capacitance (C PD ). In addition, the circuit bandwidth is enhanced with capacitive degeneration and shunt peaking techniques. With C PD of 1.5-pF, our TIA has about two times larger bandwidth compared with conventional TIAs.

The authors present a low-power 850 nm Si optoelectronic integrated circuit (OEIC) receiver fabricated in standard 65 nm complementary metal-oxide semiconductor (CMOS) technology. They analyse power consumption of previously reported CMOS OEIC receivers and determine the authors receiver architecture for low-power operation. Their OEIC receiver consists of a CMOS-compatible avalanche photodetector and electronic circuits that include an inverter-based transimpedance amplifier, a tunable equaliser and a post amplifier. With the fabricated OEIC receiver, they successfully demonstrate 8 Gb/s operation with a bit-error rate <10 −12 at incident optical power of −4.5 dBm. Their OEIC receiver consumes 5 mW with 1.2 V supply voltage. To the best of their knowledge, their OEIC receiver achieves the lowest energy efficiency among 850 nm CMOS OEIC receivers.