The emergence of vertical GaN devices solves the problem of insufficient voltage withstand capacity of horizontal GaN devices. However, the current output capability of vertical GaN devices is not comparable to that of lateral GaN devices. So we propose a Al0.3Ga0.7N/GaN current-aperture vertical electron transistor (CAVET) with a SiO2-In0.05Ga0.95N hybrid current-blocking layer (HCBL). Through simulation and in-depth study of the proposed device, the results show that the GaN/InGaN secondary channel enhances the saturation output current of the device, achieving a saturated output current (IDSS) of 985 mA/mm and a transconductance (Gm) of 256 mS/mm, which are 30% and 25% higher than that of the single-channel SiO2 CBL device, respectively. The breakdown voltage (BV) is 230 V and the on-resistance (Ron) is only 0.58 mΩ·cm2.

The positive bias temperature instability (PBTI) reliability of buried InGaAs channel n-MOSFETs with an InP barrier layer and Al 2 O 3 gate dielectric under medium field (2.7 MV/cm) and high field (5.0 MV/cm) are investigated in this paper. The Al 2 O 3 /InP interface of the insertion of an InP barrier layer has fewer interface and border traps compared to that of the Al 2 O 3 /InGaAs interface. The subthreshold slope, transconductance, and shift of V g are studied by using the direct-current I d -V g measurements under the PBTI stress. The experimental results show that the degradation of positive V g under the medium field stress is mainly caused by the acceptor trap, while the donor trap under the high field stress become dominant in the subthreshold region, which leads to the negative shift in V g . The medium field stress-induced acceptor traps are attributed by the InP barrier layer in the subthreshold region, resulting that the low leakage current can be achieved in the buried InGaAs channel n-MOSFETs with an InP barrier layer compared to the surface InGaAs channel n-MOSFETs.