Abstract-Razor is a hybrid technique for dynamic detection and correction of timing errors. A combination of error detecting circuits and micro-architectural recovery mechanisms creates a system that is robust in the face of timing errors, and can be tuned to an efficient operating point by dynamically eliminating unused timing margins. Savings from margin reclamation can be realized as per device power-efficiency improvement, or parametric yield improvement for a batch of devices. In this paper, we apply Razor to a 32 bit ARM processor with a micro-architecture design that has balanced pipeline stages with critical memory access and clock-gating enable paths. The design is fabricated on a UMC 65 nm process, using industry standard EDA tools, with a worst-case STA signoff of 724 MHz. Based on measurements on 87 samples from split-lots, we obtain 52% power reduction for the overall distribution at 1 GHz operation. We present error rate driven dynamic voltage and frequency scaling schemes where runtime adaptation to PVT variations and tolerance of fast transients is demonstrated. All Razor cells are augmented with a sticky error history bit, allowing precise diagnosis of timing errors over the execution of test vectors. We show potential for parametric yield improvement through energy-efficient operation using Razor.Index Terms-Adaptive design, dynamic voltage and frequency scaling, energy-efficient circuits, parametric yield, variation tolerance.

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We describe the implementation and silicon measurement results from a Razor-based hardware loopaccelerator (RZLA), implementing the Sobel edge-detection algorithm. We demonstrate robust operation with a large Dynamic Voltage Scaling (DVS) range achieved using 50% of the clock-period for timing-speculation. At 1GHz operating frequency, Razor DVS enables 34% energy-efficiency improvement on a per-device basis and 33% overall on the entire batch of devices.

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