This work demonstrates the effect of increasing finger number and width on the ruggedness of the nLDMOS device under test (DUT). The ruggedness or energy handling capability is analyzed by twodimensional (2-D) and three dimensional (3-D) device and circuit simulations. The set failure criterion in our study and simulation is the device temperature reaching a critical value equal to the melting point of metal-contacts. The maximum energy is calculated by considering the pass-case prior to device failure and time-integrating the drain voltage and current for the avalanche duration. Maximum avalanche energy handling capability is seen to be increased linearly with number of device fingers. UIS test was also performed on width extended multi-finger nLDMOS device structures. The simulated results provided useful approaches to predict real experimental results and contribute to their physical interpretation by identification of the mechanism of device-failure, hot-spot location and continuous temperature extraction.

In this paper, the effect of poly-gate extension on improved ruggedness of n-type LDMOS is evaluated by two-dimensional (2D) device and circuit simulation. Multi-finger dimension of ntype LDMOS is subjected to Unclamped Inductive Switching (UIS) stress test to determine its ruggedness. It is shown that the polygate extended device yields approximately 15% higher avalanche energy handling capability (Emax) as compared to that without extended poly-gate region. This work suggests that the improvement in ruggedness of the optimized design is attributed to the suppression and shift of the electric field peaks away from the critical regions. The results from simulation are found to be in good correlation with experimental UIS test results in terms of avalanche energy range, identification of the mechanism of devicefailure and hot-spot location. It is believed from the results obtained that this approach will have remarkable impact in the ruggedness if implemented for large-array devices (LAD).