Despite improved device performance over traditional PolySiON technology, high-K metal gate flow introduces additional device variations not previously seen in Poly-SiON process, especially impacting large dimensional (WxL) devices for matching critical applications. For the first time, we report a comprehensive analysis of device variations introduced from metal gate process, GDIM and GGIM, and their sensitivity to circuit layout. Design optimization and verification mechanisms are developed to mitigate metal gate process induced variations in analog matching circuits. After co-optimization, DAC Vt mismatch is reduced by 2.1X and ADC comparator speed is improved by 23.5% in the analog blocks of an advanced mobile SoC currently in production. Introductions28nm high performance mobile system-on-chip (SoC) has exceeded one billion transistors on a single chip with application processor Fmax reaching above 2.5GHz with the help of high-K metal gate process. Advanced mobile SoC consists of best-in-class CPU, GPU, DSP, audio/video accelerator, BT/WiFi, and baseband receivers/ transmitters as a complete communication system [1]. ADC and DAC in analog blocks such as baseband require most stringent device mismatch. High-K metal gate enables continuous device scaling, but the disruptive process flow introduces additional mismatch and gate resistance variations not previously observed. Hi-K metal gate process, IP design, and system integration cooptimization are essential to ensure success of high performance low power mobile SoC products. This paper describes challenges and opportunities for design optimization to achieve 2.5GHz mobile LTE MSM product 1 st to market.

No abstract