InGaAs is a promising material that can replace the current Si nMOSFET in CMOS because of its high electron mobility. To realize a high drain current density at a low supply voltage in InGaAs, the introduction of a heavily doped source is essential. We introduced an epitaxially grown n-InP source and obtained a high drain current density. However, short-channel effects were observed in a previous study; thus, we introduced extremely-thin-body III-V-OI InGaAs MOSFETs on a Si substrate. Accounting for the channel-thickness dependence, a drain current density of 2.04 A/mm at V D F 0.5 V and clear suppression of the short-channel effects were observed for a channel thickness of 10 nm.
In this study, we fabricated MOSFETs with Al2O3/InGaAs or HfO2/Al2O3/InGaAs gate stacks. The surface was subjected to nitrogen plasma and trimethylaluminum cleaning prior to low-temperature atomic layer deposition. Electron mobility was extracted using the capacitance–gate voltage (C–VG) and drain current–gate voltage (ID–VG) characteristics. We determined that the mobility decreased when the gate voltage sweeping width increased during C–VG and ID–VG measurements. In addition, we determined that the lowering of the deposition temperature to 120 °C improved the mobility of MOSFETs with HfO2/Al2O3/InGaAs gate stacks as compared with that corresponding to deposition at 300 °C. Furthermore, HfO2/Al2O3/InGaAs gate stacks with various Al2O3 thicknesses were fabricated. When the number of Al2O3 deposition cycles was more than 4, the mobility of MOSFETs with HfO2/Al2O3/InGaAs gate stacks improved, reaching the value of the Al2O3/InGaAs gate stack.
Short Abstract-High on-currents (I on ) and low off-currents (I off ) under low supply voltage are important for logic applications. A heavily doped InP source was introduced to demonstrate the existence of high I on in InGaAs MOSFETs, and I D = 2.4 mA/ m at V D = 0.5 V was observed. GaAsSb source was introduced in InGaAs tunnel FET to realize low I off . Narrow channel body was found to be essential for steep sub-threshold (SS) dependence, and a fabricated GaAsSb/InGaAs vertical tunnel FET with a 26 nm wide body showed steep SS. In addition, an InGaAs/InP super-lattice source was studied to consider the possibility of simultaneous high I on and low I off realization.
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