A 20-Gb/s full-rate clock and data recovery circuit employing a mixer-type linear phase detector and automatic frequency locking technique is described. The phase detector achieves high-speed operation by mixing the clock with the data-transition pulses, providing output proportional to the phase error. The frequency acquisition loop utilizes the data phases rather than the clock phases to distill the frequency difference, and no external reference is used in this design. Fabricated in 90-nm CMOS technology, this circuit reveals rms and peak-to-peak jitter of 480 fs and 4.22 ps in response to a 2 31 1 PRBS on the recovered clock while consuming 154 mW from a 1.5-V supply.

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A linear CDR circuit [1] manifests itself in easy modeling and minimal activity on phase adjustment under locked condition. However, linear PDs face a speed limitation at around 10Gb/s, primarily because of the required pulsewidth comparison and finite flip-flop CK-to-Q delay. Parallelism could relax the stringent speed requirement, but it also introduces other issues such as clock skews and jitters. Frequency acquisition without an external reference such as Pottbacker FD [2] and other similar approaches [3,4] require quadrature clocks, potentially leading to higher phase noise as well. This paper presents the design and analysis of a 20Gb/s full-rate CDR circuit in 90nm CMOS, which completely eliminates the conventional issues by using an alternative linear PD structure and a referenceless FD with automaticity.The presented CDR architecture is shown in Fig. 21.5.1. It incorporates a fullrate VCO, a mixer-based linear PD, an automatic FD, and the corresponding Vto-I converters. The input data passes through a chain of delay cells, providing a total delay (from V A to V E ) approximately equal to 25ps. An XOR gate examines this fixed phase difference, creating a pulse nominally equal to 25ps upon occurrence of data transitions. Acting as the reference for phase detection, this pulse sequence and the clock from the VCO are mixed subsequently. When a data edge is present, the mixer produces an output pulse whose width is proportional to the phase difference between the XOR output and the clock. This result can be used for phase alignment. Figure 21.5.2(a) illustrates the waveforms of important nodes under locked condition. During long runs, the mixer generates a periodic signal which is in phase with the clock. This signal has a zero average if the duty cycle of the clock is 50%. In other words, the mixer provides an average output proportional to the phase error between the two inputs. A V-to-I converter thus translates the voltage into current and injects it into the loop filter. As a result, the center tap V C aligns with the clock, providing perfect sampling on the falling edges for the retiming flip-flop.To achieve a truly tristate PD, CK is applied to (V/I) PD , as depicted in Fig. 21.5.2(b), where two differential pairs steer two identical current sources. Since the clock and the mixer outputs are in phase, it completely cancels out the periodic disturbance for consecutive bits. As illustrated in Fig. 21.5.2(a), I P1 , the output current of (V/I) PD , presents pure zero output during long runs. Note that the + and -pulse of I P1 on data transitions is equivalent to a 20GHz periodic phase modulation, which is rejected by the limited loop bandwidth of the CDR (≈15MHz). The average output current as a function of phase error is also depicted in Fig. 21.5.2(c), presenting a PD gain [together with (V/I) PD ] of 300µA/rad. The bandwidth comparison of the presented PD and the Hogge PD is also shown in Fig. 21.5.1. The former achieves a flat operation range of 180°from DC to 35Gb/s, whereas the latter drops dramati...