No abstract

Abstract-Due to consider the gray level spatial distribution information, some image segmentation technologies based on entropy threshold can enhance the thresholding segmentation performance. However, they still cannot distinguish image edges and noise well. Even though GLGM(gray-level & gradientmagnitude) entropy can effectively solve the problem, but it cannot segment effectively multi-objective and complex image. In this paper, a GLGM entropy fast segmentation method based on GA is presented by combining Real-code-GA and GLGM entropy, and the single threshold segmentation of GLGM entropy is further extended to multilevel threshold segmentation. Our method compared with GLGM entropy multi-threshold exhaustive method, the segmentation result obtained by our method is basically the same as the result obtained by exhaustive method.

No abstract

In this article, we propose a new framework based on dataflow graphs to abstract and analyze designs for hard-ware architectures. It is called Actors with Stretchable Access Patterns (ASAP). It can overcome some limitations of all Static Data Flow (SDF) based models like mandatory buffering between actors. This article details the fundamental contributions of ASAP. Firstly, it gives the definition of actors and their different patterns. It also illustrates the link between these notions and components written in VHDL through several examples. Secondly, it presents the main algorithms to check if a graph processes an input data stream correctly, which is called compatibility checking. Thirdly, it summarizes the principles of graph modification to enforce this correctness in case of some blocks are declared incompatible. Finally, it briefly describes our EDA tool called BlAsT which integrates the above principles, before presenting an application on a realistic FPGA design. It shows that ASAP overwhelms other models in terms of resources saving without any impact on the global latency. It also points out the ability of BlAsT to compute and to propose graph modifications and to generate the VHDL code of the whole design.