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A generally improved recycling folded cascode (IRFC) is analyzed and implemented. Analysis and comparisons among the IRFC, the original recycling folded cascode (RFC) and the conventional folded cascode (FC) are made, and it is shown that with the flexible structure of IRFC, significant enhancement in transconductance, slew rate and noise can be achieved. Prototype amplifiers were fabricated in 0.13 μm technology. Measurement shows that IRFC has 3× enhancement in gain-bandwidth and slew rate over conventional FC, and the enhancement is 1.5× when compared with the RFC.

A two-stage differential linear power amplifier (PA) fabricated by 0.18 m CMOS technology is presented. An output matching and harmonic termination network is exploited to enhance the output power, efficiency and harmonic performance. Measurements show that the designed PA reaches a saturated power of 21.1 dBm and the peak power added efficiency (PAE) is 35.4%, the power gain is 23.3 dB from a power supply of 1.8 V and the harmonics are well controlled. The total area with ESD protected PAD is 1:2 0:55 mm 2. System measurements also show that this power amplifier meets the design specifications and can be applied for RFID reader.