Retention and graduation rates for engineering disciplines are significantly lower than desired, and research literature offers many possible causes. Engineering learning communities provide the opportunity to study relationships among specific causes and to develop and evaluate activities designed to lessen their impact. This paper details an engineering learning community created to combat three common threats to academic success of engineering students: financial difficulties, math deficiencies, and the lack of a supportive engineering culture. The project tracks participants in the learning community from first year through graduation to assess the effectiveness of its activities in improving retention and graduation rates. Scholarships were made available to address the financial difficulties; tutors, mentors, study groups, and a “freshman-to-sophomore bridge” summer program were provided to address math deficiencies; cohort engineering courses, active learning techniques, required group meetings, required group study sessions, dedicated study space, and dedicated faculty advisors were used to promote a sense of community. Quantitative retention and graduation rates for the cohort are compared to other engineering groups at the same institution. Qualitative results collected via student surveys and interviews, and lessons learned by project administrators are also presented. Retention and graduation rates of the cohort are better than those of comparable groups at the same institution. Graduation rates based upon freshman math placement are also higher than comparable groups.

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In this paper we present a novel hardware architecture for real-time image compression implementing a fast, searchless iterated function system (SIFS) fractal coding method. In the proposed method and corresponding hardware architecture, domain blocks are fixed to a spatially neighboring area of range blocks in a manner similar to that given by Furao and Hasegawa. A quadtree structure, covering from 32 · 32 blocks down to 2 · 2 blocks, and even to single pixels, is used for partitioning. Coding of 2 · 2 blocks and single pixels is unique among current fractal coders. The hardware architecture contains units for domain construction, zig-zag transforms, range and domain mean computation, and a parallel domain-range match capable of concurrently generating a fractal code for all quadtree levels. With this efficient, parallel hardware architecture, the fractal encoding speed is improved dramatically. Additionally, attained compression performance remains comparable to traditional searchbased and other searchless methods. Experimental results, with the proposed hardware architecture implemented on an Altera APEX20K FPGA, show that the fractal encoder can encode a 512 · 512 · 8 image in approximately 8.36 ms operating at 32.05 MHz. Therefore, this architecture is seen as a feasible solution to real-time fractal image compression.

In this paper, the typical electrical and computer engineering (ECE) curriculum is examined to determine its effectiveness at presenting embedded programming skills. The software concepts and programming techniques necessary for embedded systems are somewhat different than those seen in other engineering domains. Thus, it makes sense to specifically address embedded programming needs within the formal programming education ECE students receive. Several topical areas of concern are identified, and two possible ways to incorporate these areas into an ECE curriculum are presented. The experiences gained within the ECE curriculum at The University of Alabama are presented and are used to develop recommendations for incorporating these topics into typical ECE curricula.