Mitogen-activated protein kinase (MAPK) pathway inhibitors show promise in treating melanoma, but are unsuccessful in achieving long-term remission. Concordant with clinical data, BRAFV600E melanoma cells eliminate glycolysis upon inhibition of BRAFV600E or MEK with the targeted therapies Vemurafenib or Trametinib, respectively. Consequently, exposure to these therapies reprograms cellular metabolism to increase mitochondrial respiration and restrain cell death commitment. As the inner mitochondrial membrane (IMM) is sub-organellar site of oxidative phosphorylation (OXPHOS), and the outer mitochondrial membrane (OMM) is the major site of anti-apoptotic BCL-2 protein function, we hypothesized that suppressing these critical mitochondrial membrane functions would be a rational approach to maximize the pro-apoptotic effect of MAPK inhibition. Here, we demonstrate that disruption of OXPHOS with the mitochondria-specific protonophore BAM15 promotes the mitochondrial pathway of apoptosis only when oncogenic MAPK signaling is inhibited. Based on RNA-sequencing analyses of nevi and primary melanoma samples, increased pro-apoptotic BCL-2 family expression positively correlates with high-risk disease suggesting a highly active anti-apoptotic BCL-2 protein repertoire likely contributes to worse outcome. Indeed, combined inhibition of the anti-apoptotic BCL-2 repertoire with BH3-mimetics, OXPHOS, and oncogenic MAPK signaling induces fulminant apoptosis and eliminates clonogenic survival. Altogether, these data suggest that dual suppression of IMM and OMM functions may unleash the normally inadequate pro-apoptotic effects of oncogenic MAPK inhibition to eradicate cancer cells, thus preventing the development of resistant disease, and ultimately, supporting long-term remission.

This paper describes the high-performance CPU design of a heterogeneous octa-core CPU complex, incorporated into a highly integrated mobile SoC for smartphone applications. The SoC is fabricated in a 28nm high-κ metal-gate CMOS, and has a die size of 89mm 2 . Cu pillars are used for the die-to-substrate interface with fine substrate trace pitch. The SoC is packaged in a 14mm×14mm, 832 ball, 0.4mm pitch BGA. An integrated cellular modem supports rel. 9, cat. 4 LTE (FDD and TDD), while additional cellular and RF connectivity includes DC-HSPA+, TD-SCDMA, EDGE, 802.11ac, Bluetooth LE, GLONASS, Beidou, Galileo & QZSS), and ANT+. Multimedia features are highlighted by a high-performance Power-VR Series6 GPU, support for WQXGA displays (2560×1600), a 20Mpixel image processor and camera interface, and ultra-HD video playback support for H.264 and VP9.The compute function of the SoC is a heterogeneous CPU complex [1] consisting of two clusters of four ARMv7 CPUs (see Fig. 23.3.1). A first cluster contains four power-efficient Cortex-A7 cores, featuring in-order execution for maximum power efficiency and a shared 512kB L2 cache. A second cluster contains four high-performance (HP) Cortex-A17 cores featuring out-of-order execution for maximum performance and a shared 2MB L2 cache. A die photograph of the SoC is shown in Fig. 23.3.7, highlighting the HP CPU cluster and L2 cache.Because smartphone applications are often limited by thermal constraints, it is critical to optimize clock speed and minimize device leakage in order to maximize performance. In the HP CPU, a clock speed of 2.5GHz is achieved using only SVT (standard V t ) transistors. This paper describes the circuit techniques used to achieve these goals.In the HP CPU implementation, a strategy is required for minimizing leakage current in low-power applications. A fully integrated power-switch, shown in Fig. 23.3.2, is controlled by a local power controller enabling seamless sequencing between five power modes: 1) external-off, 2) CPU hot-plug, 3) fast-adaptive retention with reverse body-bias, 4) CPU standby and 5) CPU forward body bias. Modes 1-3 address idle leakage, while 4-5 are active modes. Immediately after a CPU enters idle mode, such as "wait for interrupt" (WFI), the power controller lowers the voltage by engaging a diode integrated into the power switch. The diode drops the voltage to the retention level and additionally keeps the logic in reverse body-bias mode for lower leakage. When an interrupt such as a snoop request is detected, the controller restores the voltage in <1μs. Because the state and memory contents are retained, the CPU returns to active state immediately after the voltage is restored. Hot-plug mode is used if the CPU idle time is extended in which context-save-and-restore of the cache data and configuration settings is required since the power is fully discharged. When all four CPUs in the cluster are in hot-plug mode, the external PMIC removes the voltage, resulting in the lowest power mode, external-OFF.The distributed power-switc...

This paper presents evaluation results of dicing tape selection for wire-bond and flip chip wafers in a volume production assembly environment. The goal of this project is to investigate a tape with low material cost, long shelf life and minimal dicing and die picking damages. Tape selection considerations, method and an evaluation plan were established, including inspection criteria for dicing and subsequent assembly steps.

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