Planarization has become a necessity for fabricating devices, large and small. Without planarization, only a limited number of layers of interconnects or device structures can be successfully fabricated. CON-TACT planarization is a method that applies and extends the fundamentals of press planarization by utilizing external force to bring an optically flat surface in physical contact with flowable materials. The surface planarity is replicated from that of the optically flat surface to the planarized flowable material surface, which is then hardened and separated afterward from the pressing surface to achieve planarity. In this study, CON-TACT planarization technology has been utilized to planarize various polymer dielectric materials coated on both Si and GaAs topography and device wafers, resulting in both local and global planarity. The polymer materials used in this study include cyclotene, polybenzoxazole, and polyimide. The results show that a topography or step height reduction of up to 98% was achieved. Additionally, the overburden variation from die to die was also significantly reduced with this method. This performance promises great potential for CON-TACT planarization technology to provide more consistent, more reliable, and improved device performance for more sophisticated and complex device designs with higher yield.

Planarization has become a necessity for fabricating devices, large and small. Without planarization, a limited number of layers of interconnects or device structures can be successfully fabricated. CON TACT® planarization technology has been used to planarize various spin-on dielectric materials to provide both local and global planarity. Materials such as epoxies, anti-reflective coatings, photoresists, spin-on glass, CycloteneTM, polybenzoxazole, and polyimide have been successfully planarized with up to more than 98% topography reduction. Consequently, the overburden variation was reduced. The planarization performance obtained promises great potential for this technology to provide more consistent, more reliable and otherwise improved device performance for more sophisticated device designs with higher yield.