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Silicon ferroelectric field-effect transistors (FeFETs) with low-k interfacial layer (IL) between ferroelectric gate stack and silicon channel suffers from high write voltage, limited write endurance and large read-after-write latency due to early IL breakdown and charge trapping and detrapping at the interface. We demonstrate low voltage, high speed memory operation with high write endurance using an IL-free back-end-of-line (BEOL) compatible FeFET. We fabricate IL-free FeFETs with 28nm channel length and 126nm width under a thermal budget <400 0 C by integrating 5nm thick Hf0.5Zr0.5O2 gate stack with amorphous Indium Tungsten Oxide (IWO) semiconductor channel. We report 1.2V memory window and read current window of 10 5 for program and erase, write latency of 20ns with ±2V write pulses, read-after-write latency <200ns, write endurance cycles exceeding 5x10 10 and 2-bit/cell programming capability. Array-level analysis establishes IL-free BEOL FeFET as a promising candidate for logic-compatible high-performance on-chip buffer memory and multi-bit weight cell for compute-in-memory accelerators.

Analog and RF mixed-signal cryogenic-CMOS circuits with ultra-high gain-bandwidth product can address a range of applications such as interface circuits between Superconducting Single-flux Quantum (SFQ) logic and cryo-DRAM memory, circuits for sensing and controlling qubits faster than their de-coherence time for at-scale quantum processor. In this work, we evaluate RF performance of 18nm gate length (LG) FDSOI NMOS and PMOS from 300K to 5.5K operating temperature. We experimentally demonstrate extrapolated peak unity current-gain cutoff frequency (fT) of 495/337 GHz (1.35x /1.25x gain over 300K) and peak maximum oscillation frequency (fMAX) of 497/372 GHz (1.3x gain) for NMOS/PMOS, respectively, at 5.5 K. A small-signal equivalent model is developed to enable design-space exploration of RF circuits at cryogenic temperature and identify the temperature-dependent and temperatureinvariant components of the extrinsic and the intrinsic FET. Finally, performance benchmarking reveals that 22nm FDSOI cryogenic RF CMOS provides a viable option for achieving superior analog performance with giga-scale transistor integration density.

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