This paper presents a 1Tb/s 3W inter-chip transceiver. The data rate is the highest and the power dissipation is the lowest among transceiver chips reported previously at ISSCC (Fig. 23.4.1). Both clock and data are transmitted by inductive coupling. The clock frequency is 1GHz and data rate per channel is 1Gb/s. 1024 data transceivers are arranged with a pitch of 30µm. The total layout area for the clock and data transceivers is 2mm 2 in 0.18µm CMOS and the chip thickness is 10µm. Time Division Multiple Access (TDMA) using 4 phases reduces crosstalk effectively. The measured Bit Error Rate (BER) is lower than 10 -12 . Bi-Phase Modulation (BPM) is employed to improve noise immunity, resulting in reduced power dissipation in the transceiver.

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