Always an efficient and low complexity reconfigurable filter architecture is required for the channel filters of digital channelizer in software-defined radio (SDR). In this paper, a block-based reconfigurable finite impulse response (FIR) filter is proposed using distributed arithmetic (DA) technique. The complexity of the conventional multiplier is replaced with the DA multiplication process, and the throughput of the entire filter is increased by block processing. Memory reuse is also achieved in the proposed direct form systolic FIR filter architecture due to parallel processing. The different bandwidth filters and the corresponding coefficients are stored in the look-up tables (LUTs) concerning different channels of the digital channelizer. The proper channel selection is used to choose an appropriate filter and partial products are generated using offset binary coding (OBC). Next, the multiplication process is done by the proposed decomposed LUT-based DA technique in the processing blocks of the filter. The proposed filter is coded by Verilog and synthesized by application specific integrated circuit (ASIC)-based tools from Cadence in 45 nm CMOS technology. The performance parameters such as area, delay, power consumption, area-delay product (ADP), and power delay product (PDP) are evaluated and compared with state-of-the-art works. The ADP and PDP values are saved by 44.1% and 30% by the proposed OBC-DA-based filter architecture than the conventional DA-based filter architecture, respectively.

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Always an efficient and low complexity reconfigurable filter architecture is required for the channel filters of digital channelizer in Software Defined Radio (SDR). In this paper, a block-based reconfigurable FIR filter is proposed using Distributed Arithmetic (DA) Technique. The complexity of the conventional multiplier is replaced with the DA multiplication process and the throughput of the entire filter is increased by block processing. Memory reuse is also achieved in the proposed direct form systolic FIR filter architecture due to parallel processing. The different bandwidth filters and the corresponding coefficients are stored in the LUTs concerning different channels of the digital channelizer. The proper channel selection is used to choose an appropriate filter and partial products are generated using Offset Binary Coding (OBC). Next, the multiplication process is done by the proposed decomposed LUT-based DA technique in the processing blocks of the filter. The proposed filter is coded by Verilog and synthesized by ASIC-based tools from Cadence in 45 nm CMOS technology. The performance parameters such as area, delay, power consumption, ADP, and PDP are evaluated and compared with the state-of-the-art works. The ADP and PDP values are saved by 44.1% and 30% by the proposed OBC-DA-based filter architecture than the conventional DA-based filter architecture, respectively.