This paper presents two low power design techniques used for successive approximation registers (SAR) analog-to-digital converter (ADC) for transmission of Physiological signal: Dual split switching; set and reset phase. Dual split switching is used in one sided charge scaling digital-to-analog converter (DAC) to edge of the switching energy by reducing the leakage in dual transmission gate. The set and reset phase defines the amplification and comparison phase of the comparator. The delay time of the comparator is profoundly reduced with folded cascoded pre amplifier and a regenerative latch. A Serial In Parallel Out (SIPO) N bit register and SAR are designed with negative edge triggered D Flip-Flop (DFF). For power optimization the supply voltage of SAR ADC is designed with 500 mV. The Variable threshold concept has been utilized in the entire design to operate the SOC with 500 mV supply voltage. The designed SAR ADC is capable of supporting the sampling rate of 1 Msps. The circuit is designed using standard UMC 180 nm technology. The simulation results show that the power consumption of the SAR ADC is 13.99 μW and achieved 68.54 dB SFDR with ENOB value 7.69 bits. The DNL (max) is + 0.9/− 0.82 LSB and INL 1.06/− 1.31 LSB.

This paper presents a new topology to implement MOS current mod logic (MCML) tri-state buffers. In Mos current mode logic (MCML) current section is improves the performance and maintains low power of the circuit. MCML circuits contains true differential operation by which provides the feature of low noise level generation and static power dissipation. So the amount of current drawn from the power supply does not depends on the switching activity. Due to this MOS current mode logic (MCML) circuits have been useful for developing analog and mixed signal IC's. The implementing of MCML D-flip flop and Frequency divider done by using MCML D-latches. The proposed MCML D-latch consumes less power as it makes use of low power tri-state buffers. Which promotes power saving due to reduction in the overall current flow in the proposed D flip flop topology is verified though Cadence GPDK-180nM CMOS technology parameters.

This paper discusses an FPGA-based intelligent car washing system. The system provides washing services that are rapid, convenient, and effective. A flow chart for controlling an automated car washing system with four working modes is given in this paper. The car washing system was built with the help of Xilinx Vivado in the software ISE Design Suite using the hardware description language Verilog HDL. In this project, a special feature for water conservation by biologically recycling the water is implemented.

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