As transistor dimension becomes smaller and with the switch to high-k metal gate (HKMG) integration, the need for a sidewall protection layer that is conformal yet meets the low thermal budget requirement becomes critical. In this work, we evaluated PEALD SiN as spacer material in comparison to PECVD SiN, at two different stresses (compressive and tensile) and two different deposition temperatures. Material characterization reveals that PEALD SiN has lower hydrogen impurities, higher density and better resistance against wet chemistry, indicating superior material quality. In addition, film conformality and pattern density characteristics for all PEALD SiN films are significantly improved over PECVD SiN. These improvements in film characteristics help drive improvement in electrical properties for devices with PEALD SiN spacer.As transistor scaling continues and with the implementation of high-k metal gate (HKMG) in Complementary Metal-Oxide Semiconductor (CMOS), there is a critical need for a highly conformal sidewall protection layer. To prevent oxidation of the high-k layer and out diffusion of implants, the sidewall protection layer must be deposited at a relatively low deposition temperature. Furthermore, as transistor designs increase in complexity, this encapsulation layer or spacer must be conformal and not sensitive to wafer loading conditions. Traditionally, the spacer is deposited using chemical vapor deposition (CVD). 1,2 LPCVD SiN is known for having good conformality but its deposition occurs at high temperature (>700 • C). As the need arises for a spacer with a lower thermal budget, plasma enhanced CVD (PECVD) SiN has been used. With PECVD SiN, deposition temperature can be lowered to ∼400 • C. However, PECVD SiN has worse conformality compared to LPCVD SiN. Moreover, CVD processes are gas-phase reaction limited and thus the film growth is sensitive to loading conditions. As chip designs become more complex, with each chip having regions with different transistor densities, it is critical to have a spacer process that is not pattern density dependent.Atomic Layer Deposition (ALD) is a deposition technique which has a clear advantage of lower deposition temperature and excellent conformality. 3,4 The development of ALD SiN processes for various applications has been reported in the literature. Hong et al. reported ALD SiN layer and SiN/SiO 2 /SiN multi layers as a gate dielectric for flash memory. 6 For spacer application in 90 nm technology, it has been reported that using ALD SiO 2 and ALD SiN as spacer and silicide blocking layer resulted in improved short channel effects. The ALD SiN was deposited at 595 • C using dichlorosilane and NH 3 . 6 The main disadvantage of ALD compared to PECVD and LPCVD is its higher cost of ownership. This, however, is beyond the scope of this work.Plasma enhanced ALD (PEALD) has been gaining popularity and recently more new PEALD processes are being developed. 4,7-10 A comprehensive review article covering the basics of PEALD, its advantages and challenges had been ...
With the transition to ≤28-nm CMOS technology nodes, the surface analytical challenges with regard to steadily decreasing dimensions and still growing materials options raise the demand of high performing surface analysis techniques. Characterization of ultrathin films and multilayer stacks, especially in high-k metal gate stacks, by means of low energy ion scattering spectroscopy (LEIS) with its monolayer sensitivity has been established as a very useful analysis technique next to Auger electron spectroscopy, X-ray photoelectron spectroscopy, and time-of-flight secondary ion mass spectrometry. Questions regarding film nucleation, growth, coverage, and diffusion can be answered, thereby enabling those processes to be controlled appropriately.In this work, growth studies of ALD HfO 2 and TiN are shown, as well as film thickness determination based on surface spectra. PVD aluminum and lanthanum, acting as work function metals on the gate oxide, were deposited, and their film formation and closure were investigated.Further application fields of LEIS have emerged from the characterization of in-die features on patterned wafers. As presented on test arrays, it is possible to detect material deep in trenches. This is an advantage if residues need to be identified after etch or clean processes. KEYWORDS ALD, growth study, high-k metal gate, LEIS, PVD, work function metal 1 | INTRODUCTION CMOS technology progression beyond the 32-nm node requires the implementation of new materials such as high-k gate dielectrics and ultra thin metal gates. The scaling of conventional Poly SiON transistor structures is limited because of too high gate leakage currents. For 32nm CMOS and beyond, the needed short channel properties can only be reached by high-k metal gate (HKMG) technology. There are 2 integration approaches in implementing HKMG into CMOS: Gate First andGate Last. In the Gate First integration, as the name implies, the HKMG is formed first, followed by gate patterning, source/drain (S/D) and contact formation. In the Gate Last integration, a dummy gate is created, followed by gate patterning and S/D formation. The dummy gate is then removed, and the HKMG and finally the contacts are manufactured 1-6 ( Figures 1 and 2). The operation of these very complex integration schemes requires comprehensive studies, in order to define the materials and material combinations with the appropriate properties and compatibility, and the optimum work function tuning metals. Deposition processes, as well as cleaning and etching strategies, have to be developed or adapted. The properties of the ultra thin films in a HKMG stack strongly influence the transistor performance. Consequently, the introduction of atomic layer deposition (ALD) processes, replacing the established chemical, metal organic, and physical vapour deposition processes (CVD, MO-CVD, PVD), became a requirement. Key questions for the analyst are about nucleation, film growth, or diffusion. The transient regime in film formation of high-k gate oxide, metal gate, and the work f...
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