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By using CNFET technology in 3a 2 nm node using a proposed SQI gate, two split bit-lines QSRAM architectures have been suggested to address the issue of increasing demand for storage capacity in IoT/IoVT applications. Peripheral circuits such as a novel quaternary to binary decoder for QSRAM have been offered. Various simulations on temperature, supply voltage, and access frequency have been done to evaluate and ensure the performance of the proposed SQI gate, suggested cells, and quaternary to binary decoder. Moreover, 1000 Monte-Carlo analyses on the fabrication parameters have been done to classify read and write delay and standby power of proposed cells along with PDP of proposed quaternary to binary decoder. It is worth mentioning that the PDP of the proposed SQI gate, decoder, and average power consumption of suggested HF-QSRAM cell reached 0.92 aJ, 4.13 aJ, and 0.15 µW, respectively, which are approximately 80%, 91%, and 33% improvements in comparison with the best existing designs in the literature.

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