We present a capacitance-voltage study for arrays of vertical InAs nanowires. Metal-oxide-semiconductor (MOS) capacitors are obtained by insulating the nanowires with a conformal 10nm HfO2 layer and using a top Cr∕Au metallization as one of the capacitor’s electrodes. The described fabrication and characterization technique enables a systematic investigation of the carrier density in the nanowires as well as of the quality of the MOS interface.

The capacitance of arrays of vertical wrapped-gate InAs nanowires is analysed. With the help of a Poisson-Schrödinger solver, information about the doping density can be obtained directly. Further features in the measured capacitance-voltage characteristics can be attributed to the presence of surface states as well as the coexistence of electrons and holes in the wire. For both scenarios, quantitative estimates are provided. It is furthermore shown that the difference between the actual capacitance and the geometrical limit is quite large, and depends strongly on the nanowire material.

We investigate the Au-assisted growth of InAs nanowires on two different kinds of heterostructured substrates: GaAs/AlGaAs structures capped by a 50 nm thick InAs layer grown by molecular beam epitaxy and a 2 microm thick InAs buffer layer on Si(111) obtained by vapor phase epitaxy. Morphological and structural properties of substrates and nanowires are analyzed by atomic force and transmission electron microscopy. Our results indicate a promising direction for the integration of III-V nanostructures on Si-based electronics as well as for the development of novel micromechanical structures incorporating nanowires as their active elements.

We investigate the interaction between surface acoustic waves on a piezoelectric LiNbO 3 substrate and charge carriers in InAs nanowire transistors. Interdigital transducers are used to excite electromechanical waves on the chip surface and their influence on the transport in the nanowire devices is studied at room temperature. Charge pumping is studied in different biasing conditions and in pulsed operation in order to assess interference effects due to reflected waves on the sample chip. Present results constitute a key building block for the realization of acoustoelectric nanodevices based on the InAs/InP nanowire technology.