A new topology for a current-mode multi-phase sinusoidal oscillator (MSO) is introduced. It is designed using current-differencing cascaded transconductance amplifiers (CDCTAs) and operational transconductance amplifiers (OTA). Both designs realize odd and even numbers of phase oscillators. The MSO is implemented by cascading first-order all-pass filter stages that are designed with CDCTAs or OTAs and show the same transfer function. The MSO includes n grounded resistors and n grounded capacitors to generate n phases. We highlight the advantage of using OTAs because the resulting MSO circuitry is greatly reduced compared to using CDCTAs, while in both designs the high output impedances facilitate easy driving an external load without additional current buffers. The condition of oscillation and the frequency of oscillation are orthogonal and can be adjusted by varying a bias current. Finally, SPICE simulation results using integrated circuit technology of 0.35 mm show that the designed MSO provides odd/even phase signals that are equally spaced in phase and with equal amplitude.

This paper presents the high-output-impedance current-mode multiphase sinusoidal oscillators (MSO) using voltage differencing current conveyor (VDCC)-based lossy integrators, which consist of one VDCC, one grounded capacitor, and two grounded resistors. The proposed oscillator can provide an odd-phase and even-phase system without the use of an additional amplifier. The frequency of oscillation (FO) is electronically tuned via the bias current without affecting the condition of oscillation (CO). The proposed oscillator is designed to obtain three-phase sinusoidal waveforms (n = 3). The effect of non-idealities of VDCC on the lossy integrator section is also investigated. The validity of the proposed circuit is demonstrated by PSPICE simulation using 0.18 µm TSMC CMOS process parameters with ±0.9V power supply. The frequency of oscillation obtained from the simulation is 1.43 MHz. The total harmonic distortions of the sinusoidal output currents IO1, IO2, and IO2 are 1.22%, 1.18%, and 0.57%. The IO1–IO2 and IO2–IO3 phase differences are approximately 121 and 119 degrees, respectively. The feasibility of the proposed MSO is also verified with experimental results using the VDCC constructed from the commercially available ICs (LT1288 and AD844) with ±5 V power supply. The results of PSPICE simulations and experiments are closely consistent with the theoretical expectation.