With the progress of wafer level and chip scale packaging, copper pillar bump technology has been applied in advanced assembly due to the advantage of fine pitch capability, better electrical performance and lower power consumption. As one of the critical process of copper pillar bump technology, electroplating process is gaining more and more interests from the semiconductor packaging R&D community. In this work, two different electroplating processes, i.e. single-rate plating method and multi-rate plating method, have been studied. The impacts on bump height co-planarity, copper pillar profile and wafer stress are further evaluated. By applying multi-rate plating method, better copper pillar bump performance and higher electroplating efficiency can be both achieved.