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Safety-critical intelligent automotive systems require stringent dependability while the systems are in operation. Therefore, safety and reliability issues must be addressed in the development of such safety-critical systems. Nevertheless, the incorporation of safety/reliability requirements into the system will raise the design complexity considerably. Furthermore, the international safety standards only provide guidelines and lack concrete design methodology and flow. Therefore, developing an effective safety process to assist system engineers in tackling the complexity of system design and verification, while also satisfying the requirements of international safety standards, has become an important and valuable research topic. In this study, we propose a safety-oriented system hardware architecture exploration framework, which incorporates fault tree-based vulnerability analysis with safety-oriented system hardware architecture exploration to rapidly discover an efficient solution that complies with the ISO-26262 safety requirements and hardware overhead constraint. A failure mode, effect, and diagnostic analysis (FMEDA) report is generated after performing the exploration framework. The proposed framework can facilitate the system engineers in designing, assessing, and enhancing the safety/robustness of a system in a cost-effective manner.

We propose a safety-oriented design process for IP-based safety-critical system-on-chip (SoC). The proposed safety process can facilitate the measurement of the robustness based on the safety-related metrics and scales of failure-induced risks in a system that can be employed to locate the critical components for protection to effectively diminish the influence of failures on the system. The risk reduction phase is activated to enhance the robustness of critical components identified by vulnerability analysis if the measured robustness is insufficient. An SoC-level safety design platform was built on the SystemC Synopsys Platform Architect MCO to demonstrate the core idea of the safety process. The safety-oriented design process for an ARM-embedded SoC modeled at the TLM level was conducted to demonstrate the feasibility of our safety approach.