Background: The human ken and understanding about esoteric phenomenon develops the period from space to the sub-atomic level. The passion to further explore the unexplored domains and dimensions boosts the human advancement in a cyclic way. A significant part of such passion follows in the electronics industry. Moore’s law is reaching the practical limitations because of further scaling of metal oxide semiconductor (MOS) devices. The need of a more dexterous and effective technology approach is demanded. Quantum-dot cellular automata (QCA) is an emerging technology which avoids the physical limitations of the MOS device. QCA is a dynamic computational transistor paradigm that addresses device density, power, operating frequency and interconnection problems. It requires an extensive study to know the fundamentals of logic implementation. Objective: Immense research and experiments due same vigor led to the evolving nanotechnology and a feasible alternative to complementary metal oxide semiconductor (CMOS) technology. A comprehensive study is presented in the paper to enhance the basics of QCA technology and the way of implementation of the logic circuits. Different existing circuits using QCA technology are discussed and compared for different parameters. Methods: Scaling the devices can reduce the power consumption of the MOS device. Quantum dots are nanostructures made from semi-conductive conventional materials. It is possible to model these constructions as 3-dimensional (3D) quantum energy wells. Logical operations and data movement are performed using Columbic interaction between nearby QCA cells instead of current flow. Results: The focus of this review paper is to study the trends which have been proposed and compared the designs for various digital circuits. The performance of different circuits such as XOR, adder, reversible gates and flip-flops are provided. Different logic circuits are compared on the parameters such as cell count, area and latency. At least 10 QCA cells are used for the XOR gate with 1 clock latency. Minimum 44 QCA cells are required to make a full adder with 1.25 clock latency.

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Glasses have been used as the most versatile engineering materials for more than five decades. Chalcos is a Greek word which means ore former and glasses prepared by particular chalcogenide of group VI element of the periodic table or by their compounds have been known for more than 50 years as optical material. The primary objective is to provide up to date description of the development in the field of optical and electrical properties of MWCNTs additive chalcogenide glasses.An extensive survey of relevant literature was carried out using sophisticated libraries, virtual media, different research laboratories, internet and also by personal contact with the senior researcher of this field. The exponential increase in d.c. conductivity was observed on increasing the CNT concentration. Inter nanotube connections increase which results in modification of chemical bond formation with increased CNT concentration. It has been observed that the optical band gap of CNT doped chalcogenide glass increases which may be attributed to the fact that CNT added to to the glasses retards the motion of charge carriers and may raise the optical bandgap. The electrical and optical properties of CNT additives chalcogenide glasses have been reviewed. Several applications based on CNT doped glasses have also been discussed, including the development of ionic memories, sensors, optical waveguides, holography, solid-state batteries, optical, and non-linear optical devices.

Background: The increased demand of battery operated portable systems boost up the field of low power VLSI design. Integrated circuits are enhancing the performance of the systems in terms of lesser area requirement, higher functionality and faster response at lower technology nodes. The applied power supply and threshold voltage of the individual device is scaled down at lower technology node. Scaling of the threshold voltage of the devices raises the issue of leakage current. Objective: Leakage current should be made recessive with the continuous scaling of technology nodes. Methods: Various leakage current mitigation methods had been employed to reduce the leakage current at different abstraction levels. This review paper demonstrates the survey of systematic arrangement of device scaling, leakage power, its causes, and various methods to overcome the leakage current at circuit level design. Results: 3-input NAND (NAND3) gate is designed and simulated at 22 nm technology node on HSPICE tool and analyzed for comparison of different leakage reduction techniques. Conclusion: INDEP approach is the most effective approach to reduce the leakage current and improving the reliability of the circuits followed by DTCMOS technique as compared to other available techniques.