Excellent device-to-device distribution was achieved in high-performance Ni/GeO x /TiO y /TaN resistive random access memory on low-cost flexible plastics, with low 30-μW switching power (9 μA at 3 V; −1 μA at −3 V), 10 5 cycling endurance, and good retention at 85 • C. These were ascribed to bulk transport property by tunneling between traps, forming-free resistive switching, and the less destructive low power switching.Index Terms-Flexible electronics, GeO x , resistive random access memory (RRAM), TiO y .

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Narrow current distribution, good endurance, and low 28 μW switching power are successfully achieved in Ni/GeOx/TiOy/TaN resistive random access memory devices. The good distribution and endurance are attributed to the nitrogen-rich TaN to increase the oxidation resistance and decrease the TaON and oxygen vacancies formation from x-ray photoelectron spectroscopy measurements, where such oxygen vacancies are related to current conduction at high resistance state. In addition, the devices on the flexible polyimide substrate exhibit excellent mechanical endurance upon repeated bending tests, showing their high potential for low-cost flexible memory application.

To meet the requirements of flexible memory applications, we have compared two capping layers of GeOx and AlOx on a TiOy resistive random access memory (RRAM) at room temperature. A Ni/GeOx/TiOy/TaN RRAM shows a large resistance window of >102, 85 °C retention, a high-resistance-state (HRS) activation energy (Ea) of 0.52 eV, and a good DC cycling of 103 cycles, which are significantly better than those of a Ni/AlOx/TiOy/TaN RRAM, which has a high-defect-density dielectric of AlOx.

We report a low-temperature InP p-MOS with a high capacitance density of 2.7 µF/cm2, low leakage current of 0.77 A/cm2 at 1 V and tight current distribution. The high-density and low-leakage InP MOS was achieved by using high-κ TiLaO dielectric and ultra-thin SiO2 buffer layer with a thickness of less than 0.5 nm. The obtained EOT can be aggressively scaled down to < 1 nm through the use of stacked TiLaO/SiO2 dielectric, which has the potential for the future application of high mobility III-V CMOS devices.