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We present an execution model for parallel simulation of a distributed shared memory architecture. The model captures the processor-memory interaction and abstracts the memory subsystem. Using this model we show how parallel, on-line, partially-ordered memory traces can be correctly predicted without interacting with the memory subsystem. We also outline a parallel optimistic memory simulator that uses these traces, finds a global order among all events, and returns correct data and timing to each processol: A first evaluation of the amount of concurrency that our model can extract for an ideal multiprocessor shows that processors may execute relatively long instruction sequences without violating the causality constraints. Howevel; parallel simulation efJiciency is highly dependent on the memory consistency model and the application characteristics.

Abstract. In this paper we review several issues related to simulation of modem distributed shared memory architectures: workload selection and characterization, processor-memory interaction, memory simulation and simulation efficiency. These issues are discussed in the context of several modem architecture simulation workbenches. Various efficient simulation techniques are presented. In particular, we discuss the feasibility of parallel discrete event simulation techniques and argue that this is a promising approach for efficient simulation of parallel computer architectures.