Traces of heavy metals found in water resources, due to mining activities and e-waste discharge, pose a global threat. Conventional treatment processes fail to remove toxic heavy metals, such as lead, from drinking water in a resource-efficient manner when their initial concentrations are low. Here, we show that by using the yeast Saccharomyces cerevisiae we can effectively remove trace lead from water via a rapid mass transfer process, called biosorption, achieving an uptake of up to 12 mg lead per gram of biomass in solutions with initial lead concentrations below 1 part per million. Through spectroscopic analyses, we found that the yeast cell wall plays a crucial role in this process, with its mannoproteins and β-glucans being the key potential lead adsorbents. Furthermore, by employing nanomechanical characterization in the yeast biomass, we discovered that biosorption is linked to an increase in cell wall stiffness. These findings open new opportunities for using environmentally friendly and abundant biomaterials for advanced water treatment targeting emerging contaminants.

An adiabatic quantum flux parametron (AQFP) is a two-terminal superconducting device capable of amplifying or inverting digital input signals at near-kT energy dissipation. This ultra-low power device is desirable for myriad reasons, including high performance accelerator applications as CMOS processors become more and more limited by energy consumption. Promising performance results have been realized on AQFP processors; however, scaling these results to larger computing systems faces engineering challenges due to device density and power distribution. AQFP circuits require a multi-phase activation signal to propagate logic. If data is not properly aligned with the activation phase, it can be dropped or shifted to an incorrect phase and disrupt circuit operation. This work presents design and simulation of an activation phase synchronizer: a simple circuit that will accept data arriving on any phase and re-align it to a known phase of the subsequent cycle. The phase synchronizer can be useful for mitigating clock skew across clock domains or play an important role in asynchronous design where the arrival time of data may be unknown.