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We have grown various thickness Ge layers on nominal and 6 • off Si(0 0 1) substrates using a low-temperature/high-temperature strategy followed by thermal cycling. A combination of 'mounds' and a perpendicular cross-hatch were obtained on nominal surfaces. On 6 • off surfaces, three sets of lines were obtained on top of the 'mounds': one along the 1 1 0 direction perpendicular to the misorientation direction and the other two at ∼4.5 • on each side of the 1 1 0 direction parallel to the misorientation direction. The surface root mean square roughness was less than 1 nm for 2.5 μm thick nominal and 6 • off Ge layers. Those slightly tensily strained Ge layers (R ∼ 104%) were characterized by 5 × 10 7 cm −2 (as-grown layers) −10 7 cm −2 (annealed layers) threading dislocation densities, independently of the substrate orientation. We have then described the 550 • C/650 • C process used to passivate nominal Ge(0 0 1) surfaces with Si prior to gate stack deposition. An ∼5 Å thick SiGe interfacial layer is self-limitedly grown at 550 • C and then thickened at 650 • C (5 Å min −1 ) thanks to SiH 2 Cl 2 at 20 Torr. Such a Ge surface passivation yields state-of-the-art p-type metal oxide semiconductor field effect transistors provided that 15 Å Si layer thickness is not exceeded. For higher thickness, elastic strain relaxation (through the formation of numerous 2D islands) occurs, followed by plastic relaxation (for a 35 Å thick Si layer).

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