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Anisotropic etching of silicon with the hydrazine‐water mixture is studied and characterized for its practical use in integrated circuit technology. The solution is applied to {100} wafers where the etch presents a v‐shaped cross section limited at the side‐walls by {111} planes and at the bottom by a {100} plane. The etching process is evaluated in terms of the etch rate of the {100} plane, quality of side‐walls and bottom surface, and corner rounding. It is shown that the results are both concentration and temperature dependent. The optimal temperature for the etching process is found to be 100°C for both simple temperature control and high quality etching. It is also shown that the optimal mixture concentration must be choesn according to the particular use of the anisotropic etching. The optimal volume concentrations of hydrazine for the various applications are: 65% for VMOS devices and for v‐groove isolation rings, 70–80% for two‐level structures with flat bottom surface, and for electrode and sensor fabrication.

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0.4-μm-thick polycrystalline silicon deposited in a low-pressure CVD reactor was implanted with B to a dose of 5×1014/cm2 and then irradiated in a cw laser scanning apparatus. The laser annealing produced an increase in grain size from ∼500 Å to long narrow crystals of the order of ∼25×2 μ, as observed by TEM. Each grain was found to be defect free and extended all the way to the underlying Si3N4. Electrical measurements show 100% doping activity with a Hall mobility of about 45 cm2/V sec, which is close to single-crystal mobility at the same carrier concentration. Thermal annealing produces material with an average grain size of 1000 Å and a resistivity higher by a factor of 2.2 than that obtained with the laser anneal. Laser annealing performed after a thermal anneal reduces the resistivity to approximately the same value obtained by laser annealing only.

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