In Figure 5(a)-(b), the bias dependency of both drain current and S parameters are accurately captured by the neural network. In addition, a harmonic balance simulation tests the accuracy of the model for large-signal non-linear simulation. Figure 5(c) shows simulated output power for fundamental, second, and third harmonics both as a function of input power and compared with measurement beyond the 1-dB compression point. As can be seen, accurate reproduction of output power at fundamental frequency has been achieved, with second and third harmonics having a maximum error of only 2-3 dBm over the power sweep range. The power level is pushed beyond the compression point to illustrate the validity of the model under high power conditions. CONCLUSIONWe have reported a neural-network-based non-linear model for CMOS, based on capacitance, extrinsic gate, and substrate resistances parameters together with drain current. The parameters used in the model show strong dependency on bias, which are difficult to formulate accurately using empirical equation. Therefore, we have used three-layered neural network architecture to derive parameter-bias-dependent function. The developed non-linear function has then been adopted in a commercial ADS circuit simulator, using symbolically defined devices (SDD) required for implementation of the CMOS non-linear model. The non-linear mode of operation of the full model has been validated, including harmonic power, and good fits were obtained.

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