The reaction kinetics of eutectic SnPb solder on Cu were studied and compared in the liquid state at 200 to 240 °C and in the solid state aged at 125–170 °C. The ternary phase diagrams of SnPbCu, the morphology of intermetallic compound (IMC), and the kinetics of growth of the intermetallics were used in the comparison. The temperature difference between these two reactions is only 30 °C, but the kinetics of reaction, as well as the morphology of IMC formation, are very different. The kinetics in the wetting reaction is four orders of magnitude faster than that in solid state aging. The Cu6Sn5 intermetallic morphology in solid state aging is a layer type, but it has a scallop-type morphology in the wetting reaction. The morphology strongly affects the kinetics. While the kinetic difference can be attributed to the difference in atomic diffusivity between the liquid state and the solid state, it is the morphology that determines the kinetic path in these reactions. We conclude that a fast rate of reaction, which leads to a high rate of Gibbs free energy change, controls the reaction, not the Gibbs free energy change itself.

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In flip chip package applications, bumped dies are flip-chip assembled to substrate metal pads creating joints that serve electrically and mechanically. Resulting solder joint profiles are defined by the solder bump volume, the under bump metallurgy (UBM) area, and the substrate metal pad size and shape. Solder bump height and diameter was predicted by the geometrical truncated sphere model and surface evolver model at the wafer level, using the known solder volume deposited by stencil printing method. The surface evolver model was used to predict the assembled solder joint height, gap height, collapse height, and maximum bump diameter of flip chip assemblies. In turn, substrate pads were fine-tuned to achieve required gap heights. Collapse heights provided the means to develop assembly tolerances and relative risk of bridging was determined from knowledge of resulting bump diameters. Through validated design of the stencil printing technology and prediction of realistic bump and assembly solder geometries, the results are improved processes and die level design and assembly. Optimized design parameters are incorporated and accurately represented in simulation and experimentally validated with assemblies.

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