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Preparation of timetables is one of the challenges in universities. Universities are attempting to automate the timetabling process. However neither the manual nor the automated system may give a 100% accurate timetable. Therefore it is important to verify whether the requirements are satisfactorily fulfilled after generating the timetable. Authors propose a scripting language, Requirement Declarative Markup Language (RDML), for this purpose. Using RDML all user requirements can be defined and verified. Finally authors describe how to use the RDML for verifying a timetable.

Students who are beginners face difficulties in understanding basics of Computer Architecture. Their problems have been identified, and a project has been initiated to address these problems, with defined objectives.The project is to be implemented in stages: design a processor; build a simulator; develop a compiler and develop an intergraded system. The paper presents the results of the first stage -design a processor. The features and characteristics of the processor are defined and the design process is described in detail.The SEP (Students' Experimental Processor) integrates different types of architectures: Memory-Memory, Accumulator, Extended Accumulator, Stack, Register Memory, and Load Store. It can be switched to any one of them. It was modeled using VHDL and is ready to be implemented on FPGAs.The SEP will support the introductory level students to understand the characteristics of computer architectures and their operations. Future developments of Computer Architecture education using the processor are also discussed.