In power factor correction (PFC) converters, achieving both good steady-state input current waveform and fast output dynamic response is a challenge. This is due to the effect of the double-line frequency ripple present in the sensed output voltage signal which tends to distort the reference current applied to the current controller, thus leading to a distorted input current waveform. Low bandwidth (BW) voltage loop designs to reduce this input current distortion make the output dynamic response very sluggish. A digital control algorithm for the estimation of the average value of the sensed output voltage is proposed in this study to achieve low total harmonic distortion input current and fast dynamic response with a higher BW voltage loop. The proposed algorithm is computationally less intensive and requires no additional sensors or circuitry. The effectiveness of the proposed control algorithm is validated through simulation and experimental tests on a 300 W boost PFC converter prototype operating in continuous conduction mode.

A simple modified configuration of the conventional phase-shifted full-bridge (C-PSFB) converter, phase-shifted FB converter without filter inductor (PSFB-w/o-L) is proposed in this study in order to reduce the peak voltage stress on the rectifier diodes. As the proposed configuration is devoid of filter inductor, it features lighter weight and low cost. As the proposed configuration is achieved eliminating the filter inductor, the maximum voltage that comes across the rectifier diode is limited to the output voltage, thus eliminating the need for snubber circuit. Additionally, the proposed PSFB-w/o-L has the advantage of negligible duty cycle loss. A comprehensive analysis on the mechanism of the peak voltage problem across the rectifier diode in the C-PSFB is addressed and the way it is eliminated in the proposed PSFB-w/o-L is described. The detailed analysis of the operation and design consideration of the proposed PSFB-w/o-L is presented. Simulation and experimental results are presented to verify the analysis.

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A buck-boost full-bridge topology is preferred for low-input voltage, high gain, high-power battery fed front-end converter of an all-electric motor drive system. Variants of this topology feature high direct current (DC)-gain, soft switching, continuous input and output currents with a phase modulation/asymmetrical pulse width modulation (PWM) scheme. These variants exhibit a high-magnitude DC-current in the transformer primary winding for low-input voltage, high-power application leading to poor core utilisation and low-power density of the system. The operation and analysis of the converter are presented to highlight the DC-current in the transformer and to mitigate this, a hybrid control scheme (HCS) is proposed. The proposed HCS consists of a DC-current compensation (DCCC) loop to mitigate the DC-current in the transformer without altering the DCgain with no additional components and output regulation (REG) loop to regulate the output. The output REG and DCCC loops are independent of each other. Soft switching is retained with this proposed scheme. The necessity to mitigate the DC-current, analysis, and implementation of the HCS is discussed. The verification of the proposed HCS scheme in simulation and the experimental prototype is presented.

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