In the Bitcoin network, computing double SHA-256 values consumes most of the network energy. Therefore, reducing the power consumption and increasing the processing rate for the double SHA-256 algorithm is currently an important research trend. In this paper, we propose a high-data-rate low-power hardware architecture named the compact message expander (CME) double SHA-256. The CME double SHA-256 architecture combines resource sharing and fully unrolled datapath technologies to achieve both a high data rate and low power consumption. Notably, the CME algorithm utilizes the double SHA-256 input data characteristics to further reduce the hardware cost and power consumption. A review of the literature shows that the CME algorithm eliminates at least 9.68% of the 32-bit XOR gates, 16.49% of the 32-bit adders, and 16.79% of the registers required to calculate double SHA-256. We synthesized and laid out the CME double SHA-256 using CMOS 0.18 µm technology. The hardware cost of the synthesized circuit is approximately 13.88% less than that of the conventional approach. The chip layout size is 5.9mm×5.9mm, and the correctness of the circuit was verified on a real hardware platform (ZCU 102). The throughput of the proposed architecture is 61.44 Gbps on an ASIC with Rohm 180nm CMOS standard cell library and 340 Gbps on a FinFET FPGA 16nm Zynq UltraScale+ MPSoC ZCU102.

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In this work, an industrial Wireless Local Area Network (iWLAN) system used to control industrial robots (iRBs) in factory automation (FA) environments is addressed. For fast and deterministic communication, we propose a synchronous multi-user round-robin transmission protocol. To reduce the overhead caused by the conventional multiple downlink access, we also propose a low overhead Packet Division Multiple Access (PDMA) technique. The analysis and simulation results show that our proposals provide 100% and 300% better throughput than the conventional industrial Point Coordination Function (iPCF) and Space Division Multiple Access (SDMA) protocol schemes, respectively. In particular, with the control duration per iRB of being better than 100 µsec, the proposal completely satisfies the demand for fast control of FA systems. Furthermore, the hardware architecture of MAC layer of iWLAN system is also proposed and designed to successfully implement the proposed protocol.