In this paper a high resistant EMI interference CMOS operational amplifier has been designed and simulated. It is designed by implementing easy modification of the differential pair with active current load. The power amplifier seems to be leading the output voltage power with respect to the input supply given, the two stage power amplifier was designed in this current technology and results are noted below. CMOS power amplifier is a type of power amplifier designed by using CMOS transistors connected together and get the output gain of amplifier .The desired input stage can be produce using standard CMOS technologies, and it also does not requires extra levels of masking process, such as triple well, nor external components are required. Analysis and results have been provided for very large interferences, which arise from the input pin and result produced are noted precisely. Index Terms:-CMOS, Resistivity to electromagnetic interferences (EMIs), ICs, operational amplifier (Op Amp).

A low voltage power amplifier mastered by nanoscale CMOS technology has been designed for communication technology and simulated using cadence tool. Basically working of amplifier comprises of boosting up the input to produce a larger version at the output of the devices. An input signal is basically small i.e. a few millivolts to a few microvolt. The main factors concerning small signal amplifier are normally linearity of amplification and magnitude of the output signal, since the value of voltage and current are small in a small-signal amplifier, the amount of power-bearing capacity and efficiency factor are not of much consideration. An amplifier produces greater amount of voltage at the output terminal with reference to the input signal. Large-signal amplifiers, on the side basically offer enough power to the output terminal of power handling device, ranging from few watts to some nano watt. An important function of a large-signal amplifier is the power efficiency of circuit i.e. the maximum amount of power bearing capacity of the circuit, and the impedance of the output device. It is a small dimensional circuit due to the use of nanoscale technology topologies. Basically the circuit has been designed by using feedback mechanism of two stage amplifier, first is the differential amplifier which helps in differently amplifying the signal between its two inputs and the other is the common drain amplifier that helps in producing low power to this power amplifier. The circuit has been designed using 45nm technology. The main objective of the circuit is to produce circuit as minimize as possible in nanoscale or nanometres to produce circuit parameters best suited for latest miniature technology.