Low dielectric constant (low k) materials become increasingly important for microelectronics as interconnect delays limit circuit performance. One of the most promising low k candidates is carbon-incorporated SiO2 (SiOC:H). Despite the technological relevance of these materials, little is known about their atomistic structure. In order to address this issue, this letter compares structures obtained from the density functional theory to experimental data. This is done by analyzing both the calculated vibrational modes and experimental Fourier-transform infrared spectra. The resulting agreement is excellent. This can allow for future modeling of mechanical and electronic properties of low k dielectrics.

Copper electroplating for integrated circuit damascene applications typically relies on a thin, conductive seed layer to promote nucleation of feature fill and acceptable overall thickness distribution during deposition. Important to the charge-transfer exchange process occurring at the wafer surface is the potential drop within the seed layer during the early stages of plating. The effective damascene surface area, seed layer coverage, and overall resistance of thin Cu films are examined via modeling and experimental measurements. The current-carrying capability of seed-metallized trenches is calculated in terms of an effective trench resistivity and used to compare physical vapor deposition (PVD) methods with chemical vapor deposition (CVD). For a nominal 2:1 aspect ratio trench, the modeled CVD seed resistance was found to be 5× lower than that of ionized PVD and about 2.8× lower than that of ionized PVD with resputter. Wafer-level resistance probing is introduced as a useful means to assess global differences in seed layer resistance on actual patterned substrates. Initial measurements on low-density patterns confirm that PVD seed films exhibit larger increases (+24% to 78%) in resistance than CVD films (+11%) when compared to their respective planar counterparts. Results indicate that seed resistance levels on patterned damascene substrates can be significantly larger than on planar monitor wafers—an important implication for the Cu plating manufacturing process.

We present a two-dimensional, transient, tertiary current-distribution model for copper electrochemical deposition, with detailed surface chemistry kinetics for the model system of copper deposition with three representative additives; polyethylene glycol, bis-͑sodium sulfopropyl͒ disulfide, and hydrogen chloride. Values of kinetic parameters are extracted from statistically designed rotating-disk-electrode experiments using a transport-reaction model of the experimental system. The resulting surface chemistry description is combined with fundamental conservation laws, including transient mass transport, momentum transport, and potential distribution, to form the tertiary current distribution model. Two-dimensional finite element simulations of this model provide new insight into causes of film thickness variations across the wafer, including large potential variations originating from the initial seed-layer thickness ͑terminal effect͒, a nonuniform mass-transport boundary-layer thickness resulting from cell geometry, and fluctuations in the additive concentrations. An application of pulse plating is also explored. The surface chemistry and the tertiary current distribution models could potentially form useful tools for design and optimization of copper electrochemical deposition processes.

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