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The introduction of new techniques such as double patterning will reduce overlay process tolerance much faster than the rate at which critical feature dimensions are shrinking. In order to control such processes measurements with uncertainties under 0.4nm are desirable today and will become essential within the next few years. This very small error budget leads to questions about the capability of the imaging technology used in overlay tools today and to evaluation of potential replacement techniques. In this paper we will show that while imaging technology is in principle capable of meeting this requirement, the real uncertainty in overlay within devices falls well short of the levels needed. A proper comparison between techniques needs to focus on all of the possible sources of error, and especially those that cannot be simply reduced by calibration or by repeating measurements. On that basis there are more significant problems than the relative capability of different measurement techniques. We will discuss a method by which overlay within the device area can be controlled to the required tolerance.

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The feasibility of measuring overlay using small targets has been demonstrated in an earlier paper 1 . If the target is small ("smallness" being relative to the resolution of the imaging tool) then only the symmetry of its image changes with overlay offset. For our purposes the targets must be less than 5µm across, but ideally much smaller, so that they can be positioned within the active areas of real devices. These targets allow overlay variation to be tested in ways that are not possible using larger conventional target designs. In this paper we describe continued development of this technology.In our previous experimental work the targets were limited to relatively large sizes (3x3µm) by the available process tools. In this paper we report experimental results from smaller targets (down to 1x1µm) fabricated using an e-beam writer.We compare experimental results for the change of image asymmetry of these targets with overlay offset and with modeled simulations. The image of the targets depends on film properties and their design should be optimized to provide the maximum variation of image symmetry with overlay offset. Implementation of this technology on product wafers will be simplified by using an image model to optimize the target design for specific process layers. Our results show the necessary good agreement between experimental data and the model.The determination of asymmetry from the images of targets as small as 1µm allows the measurement of overlay with total measurement uncertainty as low as 2nm.