No abstract

Post implant resist strip for 45 nm and below poses challenges with regard to Si substrate loss due to oxidation and surface modification. In particular, the process to form Ultra Shallow Junctions (USJ) with high-dose implant (HDI) creates a carbonized, cross-linked crust on the surface of the resist. Removal of the implanted resist typically requires temperature-controlled and chemically aggressive approaches which can lead to excessive substrate damage. In order to ensure the desired device characteristics, this damage must be kept to a minimum, and the required optimization is dependent on highly sensitive metrology techniques. This paper reports on wafer mass loss as a direct linear measurement technique to quantify substrate loss.

No abstract

In this paper we report on mass metrology used for the characterization of different process steps (etch, clean, cavity etch, HARP deposition and CMP) of shallow trench isolation (STI) module in conventional CMOS technology. We also report on mass metrology for the characterization of plasma doping and on HfO2 high k gate dielectric deposition process. The performance of the mass balance metrology is benchmarked against state of the art metrology, including ellipsometery and Rutherford Backscattering (RBS).